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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Drenesas,cpg-mssr.yaml4 $id: "http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#"
13 On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
18 - The CPG block generates various core clocks,
27 - renesas,r7s9210-cpg-mssr # RZ/A2
28 - renesas,r8a7742-cpg-mssr # RZ/G1H
29 - renesas,r8a7743-cpg-mssr # RZ/G1M
30 - renesas,r8a7744-cpg-mssr # RZ/G1N
31 - renesas,r8a7745-cpg-mssr # RZ/G1E
32 - renesas,r8a77470-cpg-mssr # RZ/G1C
33 - renesas,r8a774a1-cpg-mssr # RZ/G2M
[all …]
/kernel/linux/linux-5.10/drivers/clk/renesas/
DMakefile5 obj-$(CONFIG_CLK_R7S9210) += r7s9210-cpg-mssr.o
8 obj-$(CONFIG_CLK_R8A7742) += r8a7742-cpg-mssr.o
9 obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
10 obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
11 obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o
12 obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o
13 obj-$(CONFIG_CLK_R8A774B1) += r8a774b1-cpg-mssr.o
14 obj-$(CONFIG_CLK_R8A774C0) += r8a774c0-cpg-mssr.o
15 obj-$(CONFIG_CLK_R8A774E1) += r8a774e1-cpg-mssr.o
18 obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/renesas/
Dhihope-rev4.dtsi95 clocks = <&cpg CPG_MOD 1005>,
96 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
97 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
98 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
99 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
100 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
101 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
102 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
103 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
104 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
[all …]
Dr8a774c0.dtsi8 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
81 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
92 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
148 clocks = <&cpg CPG_MOD 402>;
150 resets = <&cpg 402>;
164 clocks = <&cpg CPG_MOD 912>;
166 resets = <&cpg 912>;
179 clocks = <&cpg CPG_MOD 911>;
181 resets = <&cpg 911>;
194 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a77995.dtsi9 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
80 clocks = <&cpg CPG_MOD 402>;
82 resets = <&cpg 402>;
96 clocks = <&cpg CPG_MOD 912>;
98 resets = <&cpg 912>;
111 clocks = <&cpg CPG_MOD 911>;
113 resets = <&cpg 911>;
126 clocks = <&cpg CPG_MOD 910>;
128 resets = <&cpg 910>;
141 clocks = <&cpg CPG_MOD 909>;
[all …]
Dr8a77990.dtsi8 #include <dt-bindings/clock/r8a77990-cpg-mssr.h>
93 clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
105 clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
174 clocks = <&cpg CPG_MOD 402>;
176 resets = <&cpg 402>;
190 clocks = <&cpg CPG_MOD 912>;
192 resets = <&cpg 912>;
205 clocks = <&cpg CPG_MOD 911>;
207 resets = <&cpg 911>;
220 clocks = <&cpg CPG_MOD 910>;
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/
Drenesas,cpg-mssr.txt3 On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
8 - The CPG block generates various core clocks,
16 - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
17 - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
18 - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)
19 - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)
20 - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
21 - "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H)
22 - "renesas,r8a7793-cpg-mssr" for the r8a7793 SoC (R-Car M2-N)
23 - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
[all …]
Drenesas,rcar-gen2-cpg-clocks.txt1 * Renesas R-Car Gen2 Clock Pulse Generator (CPG)
3 The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs
5 The CPG also provides a Clock Domain for SoC devices, in combination with the
6 CPG Module Stop (MSTP) Clocks.
11 - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
12 - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
13 - "renesas,r8a7792-cpg-clocks" for the r8a7792 CPG
14 - "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG
15 - "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG
16 and "renesas,rcar-gen2-cpg-clocks" as a fallback.
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/renesas/
Dr8a7795.dtsi8 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
126 clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
138 clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
150 clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
162 clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
174 clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
185 clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
196 clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
207 clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
294 clocks = <&cpg CPG_MOD 402>;
[all …]
Dr8a7796.dtsi8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
137 clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
149 clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
161 clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
172 clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
183 clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
194 clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
273 clocks = <&cpg CPG_MOD 402>;
275 resets = <&cpg 402>;
289 clocks = <&cpg CPG_MOD 912>;
[all …]
Dr8a77995.dtsi9 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
80 clocks = <&cpg CPG_MOD 402>;
82 resets = <&cpg 402>;
96 clocks = <&cpg CPG_MOD 912>;
98 resets = <&cpg 912>;
111 clocks = <&cpg CPG_MOD 911>;
113 resets = <&cpg 911>;
126 clocks = <&cpg CPG_MOD 910>;
128 resets = <&cpg 910>;
141 clocks = <&cpg CPG_MOD 909>;
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dr8a7792.dtsi8 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
54 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
64 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
112 clocks = <&cpg CPG_MOD 402>;
114 resets = <&cpg 402>;
128 clocks = <&cpg CPG_MOD 912>;
130 resets = <&cpg 912>;
143 clocks = <&cpg CPG_MOD 911>;
145 resets = <&cpg 911>;
158 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7743.dtsi10 #include <dt-bindings/clock/r8a7743-cpg-mssr.h>
78 clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
97 clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
167 clocks = <&cpg CPG_MOD 912>;
169 resets = <&cpg 912>;
182 clocks = <&cpg CPG_MOD 911>;
184 resets = <&cpg 911>;
197 clocks = <&cpg CPG_MOD 910>;
199 resets = <&cpg 910>;
212 clocks = <&cpg CPG_MOD 909>;
[all …]
Dr8a7791.dtsi10 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
78 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
98 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
163 clocks = <&cpg CPG_MOD 402>;
165 resets = <&cpg 402>;
179 clocks = <&cpg CPG_MOD 912>;
181 resets = <&cpg 912>;
194 clocks = <&cpg CPG_MOD 911>;
196 resets = <&cpg 911>;
209 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7745.dtsi10 #include <dt-bindings/clock/r8a7745-cpg-mssr.h>
74 clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
84 clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
138 clocks = <&cpg CPG_MOD 912>;
140 resets = <&cpg 912>;
153 clocks = <&cpg CPG_MOD 911>;
155 resets = <&cpg 911>;
168 clocks = <&cpg CPG_MOD 910>;
170 resets = <&cpg 910>;
183 clocks = <&cpg CPG_MOD 909>;
[all …]
Dr8a7793.dtsi8 #include <dt-bindings/clock/r8a7793-cpg-mssr.h>
70 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
90 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
148 clocks = <&cpg CPG_MOD 402>;
150 resets = <&cpg 402>;
164 clocks = <&cpg CPG_MOD 912>;
166 resets = <&cpg 912>;
179 clocks = <&cpg CPG_MOD 911>;
181 resets = <&cpg 911>;
194 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7794.dtsi9 #include <dt-bindings/clock/r8a7794-cpg-mssr.h>
72 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
82 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
130 clocks = <&cpg CPG_MOD 402>;
132 resets = <&cpg 402>;
146 clocks = <&cpg CPG_MOD 912>;
148 resets = <&cpg 912>;
161 clocks = <&cpg CPG_MOD 911>;
163 resets = <&cpg 911>;
176 clocks = <&cpg CPG_MOD 910>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dr8a7792.dtsi8 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
55 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
65 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
113 clocks = <&cpg CPG_MOD 402>;
115 resets = <&cpg 402>;
129 clocks = <&cpg CPG_MOD 912>;
131 resets = <&cpg 912>;
144 clocks = <&cpg CPG_MOD 911>;
146 resets = <&cpg 911>;
159 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7791.dtsi10 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
78 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
98 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
163 clocks = <&cpg CPG_MOD 402>;
165 resets = <&cpg 402>;
179 clocks = <&cpg CPG_MOD 912>;
181 resets = <&cpg 912>;
194 clocks = <&cpg CPG_MOD 911>;
196 resets = <&cpg 911>;
209 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7745.dtsi10 #include <dt-bindings/clock/r8a7745-cpg-mssr.h>
74 clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
84 clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
138 clocks = <&cpg CPG_MOD 912>;
140 resets = <&cpg 912>;
153 clocks = <&cpg CPG_MOD 911>;
155 resets = <&cpg 911>;
168 clocks = <&cpg CPG_MOD 910>;
170 resets = <&cpg 910>;
183 clocks = <&cpg CPG_MOD 909>;
[all …]
Dr8a77470.dtsi10 #include <dt-bindings/clock/r8a77470-cpg-mssr.h>
35 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
45 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
93 clocks = <&cpg CPG_MOD 402>;
95 resets = <&cpg 402>;
109 clocks = <&cpg CPG_MOD 912>;
111 resets = <&cpg 912>;
124 clocks = <&cpg CPG_MOD 911>;
126 resets = <&cpg 911>;
139 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7793.dtsi8 #include <dt-bindings/clock/r8a7793-cpg-mssr.h>
70 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
90 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
148 clocks = <&cpg CPG_MOD 402>;
150 resets = <&cpg 402>;
164 clocks = <&cpg CPG_MOD 912>;
166 resets = <&cpg 912>;
179 clocks = <&cpg CPG_MOD 911>;
181 resets = <&cpg 911>;
194 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7794.dtsi9 #include <dt-bindings/clock/r8a7794-cpg-mssr.h>
72 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
82 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
130 clocks = <&cpg CPG_MOD 402>;
132 resets = <&cpg 402>;
146 clocks = <&cpg CPG_MOD 912>;
148 resets = <&cpg 912>;
161 clocks = <&cpg CPG_MOD 911>;
163 resets = <&cpg 911>;
176 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7742.dtsi8 #include <dt-bindings/clock/r8a7742-cpg-mssr.h>
57 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
78 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
99 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
120 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
141 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
151 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
161 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
171 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
245 clocks = <&cpg CPG_MOD 402>;
[all …]
Dr8a7743.dtsi10 #include <dt-bindings/clock/r8a7743-cpg-mssr.h>
59 clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
78 clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
142 clocks = <&cpg CPG_MOD 402>;
144 resets = <&cpg 402>;
158 clocks = <&cpg CPG_MOD 912>;
160 resets = <&cpg 912>;
173 clocks = <&cpg CPG_MOD 911>;
175 resets = <&cpg 911>;
188 clocks = <&cpg CPG_MOD 910>;
[all …]

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