| /kernel/linux/linux-5.10/Documentation/scheduler/ |
| D | sched-capacity.rst | 2 Capacity Aware Scheduling
5 1. CPU Capacity
9 ----------------
13 different performance characteristics - on such platforms, not all CPUs can be
16 CPU capacity is a measure of the performance a CPU can reach, normalized against
17 the most performant CPU in the system. Heterogeneous systems are also called
18 asymmetric CPU capacity systems, as they contain CPUs of different capacities.
20 Disparity in maximum attainable performance (IOW in maximum CPU capacity) stems
23 - not all CPUs may have the same microarchitecture (µarch).
24 - with Dynamic Voltage and Frequency Scaling (DVFS), not all CPUs may be
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| D | sched-energy.rst | 6 ---------------
10 Energy Model (EM) of the CPUs to select an energy efficient CPU for each task,
17 /!\ EAS does not support platforms with symmetric CPU topologies /!\
19 EAS operates only on heterogeneous CPU topologies (such as Arm big.LITTLE)
25 please refer to its documentation (see Documentation/power/energy-model.rst).
29 -----------------------------
32 - energy = [joule] (resource like a battery on powered devices)
33 - power = energy/time = [joule/second] = [watt]
39 --------------------
45 -----------
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/ |
| D | cpu-capacity.txt | 2 ARM CPUs capacity bindings
6 1 - Introduction
15 2 - CPU capacity definition
18 CPU capacity is a number that provides the scheduler information about CPUs
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
25 CPU capacities are obtained by running a suitable benchmark. This binding makes
27 final capacity should, however, be:
29 * A "single-threaded" or CPU affine benchmark
30 * Divided by the running frequency of the CPU executing the benchmark
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| D | cpus.txt | 6 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
7 defining properties for every cpu.
9 Bindings for CPU nodes follow the Devicetree Specification, available from:
13 with updates for 32-bit and 64-bit ARM systems provided in this document.
22 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
26 cpus and cpu node bindings definition
30 requires the cpus and cpu nodes to be present and contain the properties
33 - cpus node
35 Description: Container of cpu nodes
41 - #address-cells
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | cpu-capacity.txt | 2 ARM CPUs capacity bindings
6 1 - Introduction
15 2 - CPU capacity definition
18 CPU capacity is a number that provides the scheduler information about CPUs
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
25 CPU capacities are obtained by running a suitable benchmark. This binding makes
27 final capacity should, however, be:
29 * A "single-threaded" or CPU affine benchmark
30 * Divided by the running frequency of the CPU executing the benchmark
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| /kernel/linux/linux-5.10/arch/arm/kernel/ |
| D | topology.c | 15 #include <linux/cpu.h>
29 #include <asm/cpu.h>
34 * cpu capacity scale management
38 * cpu capacity table
39 * This per cpu data structure describes the relative capacity of each core.
40 * On a heteregenous system, cores don't have the same computation capacity
42 * can take this difference into account during load balance. A per cpu
43 * structure is preferred because each CPU updates its own cpu_capacity field
61 * is used to compute the capacity of a CPU.
66 {"arm,cortex-a15", 3891},
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| /kernel/linux/linux-4.19/arch/arm/kernel/ |
| D | topology.c | 15 #include <linux/cpu.h>
29 #include <asm/cpu.h>
34 * cpu capacity scale management
38 * cpu capacity table
39 * This per cpu data structure describes the relative capacity of each core.
40 * On a heteregenous system, cores don't have the same computation capacity
42 * can take this difference into account during load balance. A per cpu
43 * structure is preferred because each CPU updates its own cpu_capacity field
61 * is used to compute the capacity of a CPU.
66 {"arm,cortex-a15", 3891},
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| /kernel/linux/linux-4.19/drivers/base/ |
| D | arch_topology.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Arch specific cpu topology information
11 #include <linux/cpu.h>
36 void topology_set_cpu_scale(unsigned int cpu, unsigned long capacity) in topology_set_cpu_scale() argument
38 per_cpu(cpu_scale, cpu) = capacity; in topology_set_cpu_scale()
45 struct cpu *cpu = container_of(dev, struct cpu, dev); in cpu_capacity_show() local
47 return sprintf(buf, "%lu\n", topology_get_cpu_scale(NULL, cpu->dev.id)); in cpu_capacity_show()
55 struct cpu *cpu = container_of(dev, struct cpu, dev); in cpu_capacity_store() local
56 int this_cpu = cpu->dev.id; in cpu_capacity_store()
68 return -EINVAL; in cpu_capacity_store()
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | exynos5420-cpus.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos5420 SoC cpu device tree source
9 * boards: CPU[0123] being the A15.
11 * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
14 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
16 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
17 * from the LITTLE: Cortex-A7.
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu0: cpu@0 {
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| D | exynos5422-cpus.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos5422 SoC cpu device tree source
8 * This file provides desired ordering for Exynos5422: CPU[0123] being the A7.
10 * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
15 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
16 * from the LITTLE: Cortex-A7.
21 #address-cells = <1>;
22 #size-cells = <0>;
24 cpu0: cpu@100 {
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | exynos5420-cpus.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * SAMSUNG EXYNOS5420 SoC cpu device tree source
9 * boards: CPU[0123] being the A15.
11 * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
14 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
16 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
17 * from the LITTLE: Cortex-A7.
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu0: cpu@0 {
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| D | exynos5422-cpus.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * SAMSUNG EXYNOS5422 SoC cpu device tree source
8 * This file provides desired ordering for Exynos5422: CPU[0123] being the A7.
10 * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
15 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
16 * from the LITTLE: Cortex-A7.
21 #address-cells = <1>;
22 #size-cells = <0>;
24 cpu0: cpu@100 {
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| /kernel/linux/linux-5.10/kernel/sched/ |
| D | core_ctl.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
9 #include <linux/cpu.h>
58 unsigned int cpu; member
91 return -EINVAL; in store_min_cpus()
93 state->min_cpus = min(val, state->max_cpus); in store_min_cpus()
101 return sysfs_emit(buf, "%u\n", state->min_cpus); in show_min_cpus()
110 return -EINVAL; in store_max_cpus()
112 val = min(val, state->num_cpus); in store_max_cpus()
113 state->max_cpus = val; in store_max_cpus()
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| D | sched_avg.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012, 2015-2021, The Linux Foundation. All rights reserved.
43 int cpu; in sched_get_nr_running_avg() local
45 u64 period = curr_time - last_get_time; in sched_get_nr_running_avg()
52 for_each_possible_cpu(cpu) { in sched_get_nr_running_avg()
56 spin_lock_irqsave(&per_cpu(nr_lock, cpu), flags); in sched_get_nr_running_avg()
58 diff = curr_time - per_cpu(last_time, cpu); in sched_get_nr_running_avg()
61 tmp_nr = per_cpu(nr_prod_sum, cpu); in sched_get_nr_running_avg()
62 tmp_nr += per_cpu(nr, cpu) * diff; in sched_get_nr_running_avg()
65 tmp_misfit = per_cpu(nr_big_prod_sum, cpu); in sched_get_nr_running_avg()
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| D | fair.c | 1 // SPDX-License-Identifier: GPL-2.0
55 * Targeted preemption latency for CPU-bound tasks:
58 * 'timeslice length' - timeslices in CFS are of variable length
59 * and have no persistent notion like in traditional, time-slice
63 * run vmstat and monitor the context-switches (cs) field)
71 * The initial- and re-scaling of tunables is configurable
75 * SCHED_TUNABLESCALING_NONE - unscaled, always *1
76 * SCHED_TUNABLESCALING_LOG - scaled logarithmical, *1+ilog(ncpus)
77 * SCHED_TUNABLESCALING_LINEAR - scaled linear, *ncpus
84 * Minimal preemption granularity for CPU-bound tasks:
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| /kernel/linux/linux-5.10/drivers/base/ |
| D | arch_topology.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Arch specific cpu topology information
10 #include <linux/cpu.h>
61 void topology_set_cpu_scale(unsigned int cpu, unsigned long capacity) in topology_set_cpu_scale() argument
63 per_cpu(cpu_scale, cpu) = capacity; in topology_set_cpu_scale()
71 int cpu; in topology_set_thermal_pressure() local
73 for_each_cpu(cpu, cpus) in topology_set_thermal_pressure()
74 WRITE_ONCE(per_cpu(thermal_pressure, cpu), th_pressure); in topology_set_thermal_pressure()
81 struct cpu *cpu = container_of(dev, struct cpu, dev); in cpu_capacity_show() local
83 return sysfs_emit(buf, "%lu\n", topology_get_cpu_scale(cpu->dev.id)); in cpu_capacity_show()
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/amlogic/ |
| D | meson-g12b.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12.dtsi"
13 #address-cells = <0x2>;
14 #size-cells = <0x0>;
16 cpu-map {
19 cpu = <&cpu0>;
23 cpu = <&cpu1>;
29 cpu = <&cpu100>;
33 cpu = <&cpu101>;
37 cpu = <&cpu102>;
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/qcom/ |
| D | sdm660.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
11 interrupt-parent = <&intc>;
13 #address-cells = <2>;
14 #size-cells = <2>;
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
22 clock-frequency = <19200000>;
23 clock-output-names = "xo_board";
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/arm/ |
| D | juno-r2.dts | 9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
13 #include "juno-cs-r1r2.dtsi"
17 compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
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| D | juno.dts | 4 * Copyright (c) 2013-2014 ARM Ltd.
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
26 stdout-path = "serial0:115200n8";
30 compatible = "arm,psci-0.2";
35 #address-cells = <2>;
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| D | juno-r1.dts | 9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
13 #include "juno-cs-r1r2.dtsi"
17 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
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| /kernel/linux/linux-4.19/arch/arm64/boot/dts/arm/ |
| D | juno-r2.dts | 9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
13 #include "juno-cs-r1r2.dtsi"
17 compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
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| D | juno-r1.dts | 9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
13 #include "juno-cs-r1r2.dtsi"
17 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
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| D | juno.dts | 4 * Copyright (c) 2013-2014 ARM Ltd.
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
26 stdout-path = "serial0:115200n8";
30 compatible = "arm,psci-0.2";
35 #address-cells = <2>;
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| /kernel/linux/linux-5.10/include/linux/sched/ |
| D | sd_flags.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sched-domains (multiprocessor balancing) flag declarations.
29 * certain level (e.g. domain starts spanning CPUs outside of the base CPU's
78 * Consider waking task on waking CPU.
85 * Domain members have different CPU capacities
89 * NEEDS_GROUPS: Per-CPU capacity is asymmetric between groups.
94 * Domain members share CPU capacity (i.e. SMT)
97 * CPU capacity.
98 * NEEDS_GROUPS: Capacity is shared between groups.
103 * Domain members share CPU package resources (i.e. caches)
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