| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | axm5516-cpus.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * arch/arm/boot/dts/axm5516-cpus.dtsi
10 #address-cells = <1>;
11 #size-cells = <0>;
13 cpu-map {
16 cpu = <&CPU0>;
19 cpu = <&CPU1>;
22 cpu = <&CPU2>;
25 cpu = <&CPU3>;
30 cpu = <&CPU4>;
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| D | bcm2837.dtsi | 2 #include "bcm2835-common.dtsi"
3 #include "bcm2835-rpi-common.dtsi"
11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
14 compatible = "brcm,bcm2836-l1-intc";
16 interrupt-controller;
17 #interrupt-cells = <2>;
18 interrupt-parent = <&local_intc>;
22 arm-pmu {
23 compatible = "arm,cortex-a53-pmu";
24 interrupt-parent = <&local_intc>;
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | axm5516-cpus.dtsi | 2 * arch/arm/boot/dts/axm5516-cpus.dtsi
14 #address-cells = <1>;
15 #size-cells = <0>;
17 cpu-map {
20 cpu = <&CPU0>;
23 cpu = <&CPU1>;
26 cpu = <&CPU2>;
29 cpu = <&CPU3>;
34 cpu = <&CPU4>;
37 cpu = <&CPU5>;
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| D | bcm2837.dtsi | 9 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
12 compatible = "brcm,bcm2836-l1-intc";
14 interrupt-controller;
15 #interrupt-cells = <2>;
16 interrupt-parent = <&local_intc>;
20 arm-pmu {
21 compatible = "arm,cortex-a53-pmu";
22 interrupt-parent = <&local_intc>;
27 compatible = "arm,armv7-timer";
28 interrupt-parent = <&local_intc>;
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/ |
| D | cpus.txt | 6 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
7 defining properties for every cpu.
9 Bindings for CPU nodes follow the Devicetree Specification, available from:
13 with updates for 32-bit and 64-bit ARM systems provided in this document.
22 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
26 cpus and cpu node bindings definition
30 requires the cpus and cpu nodes to be present and contain the properties
33 - cpus node
35 Description: Container of cpu nodes
41 - #address-cells
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| D | topology.txt | 6 1 - Introduction
12 - cluster
13 - core
14 - thread
16 The cpu nodes (bindings defined in [1]) represent the devices that
20 symmetric multi-threading (SMT) is supported or not.
22 For instance in a system where CPUs support SMT, "cpu" nodes represent all
24 In systems where SMT is not supported "cpu" nodes represent all cores present
27 ARM topology bindings allow one to associate cpu nodes with hierarchical groups
36 If not stated otherwise, whenever a reference to a cpu node phandle is made its
[all …]
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| /kernel/linux/linux-5.10/drivers/soc/renesas/ |
| D | r9a06g032-smp.c | 1 // SPDX-License-Identifier: GPL-2.0
8 * Derived from actions,s500-smp
17 * The second CPU is parked in ROM at boot time. It requires waking it after
20 * So the default value of the "cpu-release-addr" corresponds to BOOTADDR...
25 * So for NONSEC mode, the bootloader re-parks the second CPU into a pen
26 * in SRAM, and changes the "cpu-release-addr" of linux's DT to a SRAM address,
35 r9a06g032_smp_boot_secondary(unsigned int cpu, in r9a06g032_smp_boot_secondary() argument
39 return -ENODEV; in r9a06g032_smp_boot_secondary()
44 arch_send_wakeup_ipi_mask(cpumask_of(cpu)); in r9a06g032_smp_boot_secondary()
54 int ret = -EINVAL, dns; in r9a06g032_smp_prepare_cpus()
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| /kernel/linux/linux-4.19/drivers/soc/renesas/ |
| D | r9a06g032-smp.c | 1 // SPDX-License-Identifier: GPL-2.0
8 * Derived from actions,s500-smp
17 * The second CPU is parked in ROM at boot time. It requires waking it after
20 * So the default value of the "cpu-release-addr" corresponds to BOOTADDR...
25 * So for NONSEC mode, the bootloader re-parks the second CPU into a pen
26 * in SRAM, and changes the "cpu-release-addr" of linux's DT to a SRAM address,
35 r9a06g032_smp_boot_secondary(unsigned int cpu, in r9a06g032_smp_boot_secondary() argument
39 return -ENODEV; in r9a06g032_smp_boot_secondary()
44 arch_send_wakeup_ipi_mask(cpumask_of(cpu)); in r9a06g032_smp_boot_secondary()
54 int ret = -EINVAL, dns; in r9a06g032_smp_prepare_cpus()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | cpus.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15 defining properties for every cpu.
17 Bindings for CPU nodes follow the Devicetree Specification, available from:
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
34 cpus and cpu node bindings definition
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/cpu/ |
| D | cpu-topology.txt | 2 CPU topology binding description
6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
20 For instance in a system where CPUs support SMT, "cpu" nodes represent all
22 In systems where SMT is not supported "cpu" nodes represent all cores present
25 CPU topology bindings allow one to associate cpu nodes with hierarchical groups
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/arm/ |
| D | foundation-v8-spin-table.dtsi | 8 enable-method = "spin-table";
9 cpu-release-addr = <0x0 0x8000fff8>;
13 enable-method = "spin-table";
14 cpu-release-addr = <0x0 0x8000fff8>;
18 enable-method = "spin-table";
19 cpu-release-addr = <0x0 0x8000fff8>;
23 enable-method = "spin-table";
24 cpu-release-addr = <0x0 0x8000fff8>;
|
| D | rtsm_ve-aemv8a.dts | 1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
36 #address-cells = <2>;
37 #size-cells = <0>;
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| /kernel/linux/linux-4.19/arch/arm64/boot/dts/arm/ |
| D | foundation-v8-spin-table.dtsi | 8 enable-method = "spin-table";
9 cpu-release-addr = <0x0 0x8000fff8>;
13 enable-method = "spin-table";
14 cpu-release-addr = <0x0 0x8000fff8>;
18 enable-method = "spin-table";
19 cpu-release-addr = <0x0 0x8000fff8>;
23 enable-method = "spin-table";
24 cpu-release-addr = <0x0 0x8000fff8>;
|
| D | rtsm_ve-aemv8a.dts | 1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
15 #include "rtsm_ve-motherboard.dtsi"
20 interrupt-parent = <&gic>;
21 #address-cells = <2>;
22 #size-cells = <2>;
34 #address-cells = <2>;
35 #size-cells = <0>;
37 cpu@0 {
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/toshiba/ |
| D | tmpv7708.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * (C) Copyright 2018 - 2020, Toshiba Corporation.
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 /memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */
17 #address-cells = <2>;
18 #size-cells = <2>;
21 #address-cells = <1>;
22 #size-cells = <0>;
24 cpu-map {
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| /kernel/linux/linux-5.10/arch/arm64/kernel/ |
| D | smp_spin_table.c | 1 // SPDX-License-Identifier: GPL-2.0-only
43 static int smp_spin_table_cpu_init(unsigned int cpu) in smp_spin_table_cpu_init() argument
48 dn = of_get_cpu_node(cpu, NULL); in smp_spin_table_cpu_init()
50 return -ENODEV; in smp_spin_table_cpu_init()
53 * Determine the address from which the CPU is polling. in smp_spin_table_cpu_init()
55 ret = of_property_read_u64(dn, "cpu-release-addr", in smp_spin_table_cpu_init()
56 &cpu_release_addr[cpu]); in smp_spin_table_cpu_init()
58 pr_err("CPU %d: missing or invalid cpu-release-addr property\n", in smp_spin_table_cpu_init()
59 cpu); in smp_spin_table_cpu_init()
66 static int smp_spin_table_cpu_prepare(unsigned int cpu) in smp_spin_table_cpu_prepare() argument
[all …]
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| /kernel/linux/linux-4.19/arch/arm64/kernel/ |
| D | smp_spin_table.c | 54 static int smp_spin_table_cpu_init(unsigned int cpu) in smp_spin_table_cpu_init() argument
59 dn = of_get_cpu_node(cpu, NULL); in smp_spin_table_cpu_init()
61 return -ENODEV; in smp_spin_table_cpu_init()
64 * Determine the address from which the CPU is polling. in smp_spin_table_cpu_init()
66 ret = of_property_read_u64(dn, "cpu-release-addr", in smp_spin_table_cpu_init()
67 &cpu_release_addr[cpu]); in smp_spin_table_cpu_init()
69 pr_err("CPU %d: missing or invalid cpu-release-addr property\n", in smp_spin_table_cpu_init()
70 cpu); in smp_spin_table_cpu_init()
77 static int smp_spin_table_cpu_prepare(unsigned int cpu) in smp_spin_table_cpu_prepare() argument
81 if (!cpu_release_addr[cpu]) in smp_spin_table_cpu_prepare()
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/ |
| D | s32v234.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
4 * Copyright 2016-2018 NXP
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
23 #address-cells = <2>;
24 #size-cells = <0>;
26 cpu0: cpu@0 {
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| /kernel/linux/linux-5.10/arch/arm/mach-sti/ |
| D | platsmp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-sti/platsmp.c
8 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
30 static int sti_boot_secondary(unsigned int cpu, struct task_struct *idle) in sti_boot_secondary() argument
35 * Secondary CPU is initialised and started by a U-BOOTROM firmware. in sti_boot_secondary()
36 * Secondary CPU is spinning and waiting for a write at cpu_strt_ptr. in sti_boot_secondary()
54 int cpu; in sti_smp_prepare_cpus() local
56 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); in sti_smp_prepare_cpus()
67 for_each_possible_cpu(cpu) { in sti_smp_prepare_cpus()
69 np = of_get_cpu_node(cpu, NULL); in sti_smp_prepare_cpus()
[all …]
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| /kernel/linux/linux-4.19/arch/powerpc/boot/dts/ |
| D | iss4xx-mpic.dts | 15 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
22 model = "ibm,iss-4xx";
23 compatible = "ibm,iss-4xx";
24 dcr-parent = <&{/cpus/cpu@0}>;
31 #address-cells = <1>;
32 #size-cells = <0>;
34 cpu@0 {
35 device_type = "cpu";
[all …]
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| /kernel/linux/linux-5.10/arch/powerpc/boot/dts/ |
| D | iss4xx-mpic.dts | 15 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
22 model = "ibm,iss-4xx";
23 compatible = "ibm,iss-4xx";
24 dcr-parent = <&{/cpus/cpu@0}>;
31 #address-cells = <1>;
32 #size-cells = <0>;
34 cpu@0 {
35 device_type = "cpu";
[all …]
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| /kernel/linux/linux-4.19/Documentation/translations/zh_CN/arm64/ |
| D | booting.txt | 12 ---------------------------------------------------------------------
26 ---------------------------------------------------------------------
36 AArch64 异常模型由多个异常级（EL0 - EL3）组成，对于 EL0 和 EL1 异常级
41 这个术语来定义在将控制权交给 Linux 内核前 CPU 上执行的所有软件。
54 -----------------
65 ---------------
77 -------------
87 -------------
107 - 自 v3.17 起，除非另有说明，所有域都是小端模式。
109 - code0/code1 负责跳转到 stext.
[all …]
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| /kernel/linux/linux-5.10/Documentation/translations/zh_CN/arm64/ |
| D | booting.txt | 12 ---------------------------------------------------------------------
26 ---------------------------------------------------------------------
36 AArch64 异常模型由多个异常级（EL0 - EL3）组成，对于 EL0 和 EL1 异常级
41 这个术语来定义在将控制权交给 Linux 内核前 CPU 上执行的所有软件。
54 -----------------
65 ---------------
77 -------------
87 -------------
107 - 自 v3.17 起，除非另有说明，所有域都是小端模式。
109 - code0/code1 负责跳转到 stext.
[all …]
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| /kernel/linux/linux-4.19/arch/arm/mach-sti/ |
| D | platsmp.c | 2 * arch/arm/mach-sti/platsmp.c
7 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
40 static void sti_secondary_init(unsigned int cpu) in sti_secondary_init() argument
46 write_pen_release(-1); in sti_secondary_init()
55 static int sti_boot_secondary(unsigned int cpu, struct task_struct *idle) in sti_boot_secondary() argument
67 * the holding pen - release it, then wait for it to flag in sti_boot_secondary()
70 * Note that "pen_release" is the hardware CPU ID, whereas in sti_boot_secondary()
71 * "cpu" is Linux's internal ID. in sti_boot_secondary()
73 write_pen_release(cpu_logical_map(cpu)); in sti_boot_secondary()
76 * Send the secondary CPU a soft interrupt, thereby causing in sti_boot_secondary()
[all …]
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| /kernel/linux/linux-5.10/arch/sh/kernel/cpu/sh2/ |
| D | smp-j2.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2016 Smart Energy Instruments, Inc.
23 unsigned cpu = hard_smp_processor_id(); in j2_ipi_interrupt_handler() local
24 volatile unsigned *pmsg = &per_cpu(j2_ipi_messages, cpu); in j2_ipi_interrupt_handler()
48 np = of_find_compatible_node(NULL, NULL, "jcore,ipi-controller"); in j2_prepare_cpus()
57 np = of_find_compatible_node(NULL, NULL, "jcore,cpuid-mmio"); in j2_prepare_cpus()
79 static void j2_start_cpu(unsigned int cpu, unsigned long entry_point) in j2_start_cpu() argument
83 void __iomem *release, *initpc; in j2_start_cpu() local
85 if (!cpu) return; in j2_start_cpu()
87 np = of_get_cpu_node(cpu, NULL); in j2_start_cpu()
[all …]
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