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Searched +full:cros +full:- +full:ec +full:- +full:spi +full:- +full:msg +full:- +full:delay (Results 1 – 15 of 15) sorted by relevance

/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mfd/
Dgoogle,cros-ec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/google,cros-ec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Benson Leung <bleung@chromium.org>
11 - Enric Balletbo i Serra <enric.balletbo@collabora.com>
12 - Guenter Roeck <groeck@chromium.org>
15 Google's ChromeOS EC is a microcontroller which talks to the AP and
17 The EC can be connected through various interfaces (I2C, SPI, and others)
23 - description:
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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/mfd/
Dcros-ec.txt3 Google's ChromeOS EC is a Cortex-M device which talks to the AP and
6 The EC can be connect through various means (I2C, SPI, LPC) and the
8 its own driver which connects to the top level interface-agnostic EC driver.
9 Other Linux driver (such as cros-ec-keyb for the matrix keyboard) connect to
10 the top-level driver.
13 - compatible: "google,cros-ec-i2c"
14 - reg: I2C slave address
16 Required properties (SPI):
17 - compatible: "google,cros-ec-spi"
18 - reg: SPI chip select
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/kernel/linux/linux-4.19/drivers/platform/chrome/
Dcros_ec_spi.c2 * ChromeOS EC multi-function device (SPI)
16 #include <linux/delay.h>
24 #include <linux/spi/spi.h>
31 * Number of EC preamble bytes we read at a time. Since it takes
32 * about 400-500us for the EC to respond there is not a lot of
33 * point in tuning this. If the EC could respond faster then
36 * SPI transfer size is 256 bytes, so at 5MHz we need a response
42 * Allow for a long time for the EC to respond. We support i2c
58 * for this, clocking in at 2-3ms.
63 * Time between raising the SPI chip select (for the end of a
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/kernel/linux/linux-5.10/drivers/platform/chrome/
Dcros_ec_spi.c1 // SPDX-License-Identifier: GPL-2.0
2 // SPI interface for ChromeOS Embedded Controller
6 #include <linux/delay.h>
14 #include <linux/spi/spi.h>
23 * Number of EC preamble bytes we read at a time. Since it takes
24 * about 400-500us for the EC to respond there is not a lot of
25 * point in tuning this. If the EC could respond faster then
28 * SPI transfer size is 256 bytes, so at 5MHz we need a response
34 * Allow for a long time for the EC to respond. We support i2c
50 * for this, clocking in at 2-3ms.
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/kernel/linux/linux-4.19/include/linux/mfd/
Dcros_ec.h2 * ChromeOS EC multi-function device
29 * The EC is unresponsive for a time after a reboot command. Add a
30 * simple delay to make sure that the bus stays locked.
35 * Max bus-specific overhead incurred by request/responses.
38 * SPI requires up to 32 additional bytes for responses.
45 * Command interface between EC and AP, for LPC, I2C and SPI interfaces.
65 * @insize: Max number of bytes to accept from EC
66 * @result: EC's response to the command (separate from communication failure)
67 * @data: Where to put the incoming data from EC and outgoing data to EC
79 * struct cros_ec_device - Information about a ChromeOS EC device
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Dcros_ec_commands.h2 * Host communication command constants for ChromeOS EC
15 * The ChromeOS EC multi function device is used to mux all the requests
16 * to the EC device for its multiple features: keyboard controller,
19 * NOTE: This file is copied verbatim from the ChromeOS EC Open Source
55 /* The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff
61 /* EC command register bit functions */
63 #define EC_LPC_CMDR_PENDING (1 << 1) /* Write pending to EC */
64 #define EC_LPC_CMDR_BUSY (1 << 2) /* EC is busy processing a command */
75 #define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors 0x00 - 0x0f */
76 #define EC_MEMMAP_FAN 0x10 /* Fan speeds 0x10 - 0x17 */
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/kernel/linux/linux-5.10/include/linux/platform_data/
Dcros_ec_proto.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 * The EC is unresponsive for a time after a reboot command. Add a
26 * simple delay to make sure that the bus stays locked.
31 * Max bus-specific overhead incurred by request/responses.
34 * SPI requires up to 32 additional bytes for responses.
41 * Command interface between EC and AP, for LPC, I2C and SPI interfaces.
58 * struct cros_ec_command - Information about a ChromeOS EC command.
62 * @insize: Max number of bytes to accept from the EC.
63 * @result: EC's response to the command (separate from communication failure).
64 * @data: Where to put the incoming data from EC and outgoing data to EC.
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Dcros_ec_commands.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Host communication command constants for ChromeOS EC
7 * NOTE: This file is auto-generated from ChromeOS EC Open Source code from
8 * https://chromium.googlesource.com/chromiumos/platform/ec/+/master/include/ec_commands.h
11 /* Host communication command constants for Chrome EC */
52 * The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff
59 /* EC command register bit functions */
61 #define EC_LPC_CMDR_PENDING BIT(1) /* Write pending to EC */
62 #define EC_LPC_CMDR_BUSY BIT(2) /* EC is busy processing a command */
73 #define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors 0x00 - 0x0f */
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/mediatek/
Dmt8173-elm.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/regulator/dlg,da9211-regulator.h>
9 #include <dt-bindings/gpio/gpio.h>
19 compatible = "pwm-backlight";
21 power-supply = <&bl_fixed_reg>;
22 enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>;
24 pinctrl-names = "default";
25 pinctrl-0 = <&disp_pwm0_pins>;
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dtegra124-nyan.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
13 stdout-path = "serial0:115200n8";
19 * missing a unit-address. However, the bootloader on these Chromebook
21 * Adding the unit-address causes the bootloader to create a /memory
33 /delete-node/ memory@80000000;
39 vdd-supply = <&vdd_3v3_hdmi>;
40 pll-supply = <&vdd_hdmi_pll>;
41 hdmi-supply = <&vdd_5v0_hdmi>;
43 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
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Dtegra124-venice2.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
18 stdout-path = "serial0:115200n8";
29 vdd-supply = <&vdd_3v3_hdmi>;
30 pll-supply = <&vdd_hdmi_pll>;
31 hdmi-supply = <&vdd_5v0_hdmi>;
33 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
34 nvidia,hpd-gpio =
41 avdd-io-hdmi-dp-supply = <&vdd_1v05_run>;
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/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dtegra124-nyan.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
13 stdout-path = "serial0:115200n8";
19 * missing a unit-address. However, the bootloader on these Chromebook
21 * Adding the unit-address causes the bootloader to create a /memory
33 /delete-node/ memory@80000000;
39 vdd-supply = <&vdd_3v3_hdmi>;
40 pll-supply = <&vdd_hdmi_pll>;
41 hdmi-supply = <&vdd_5v0_hdmi>;
43 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
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Dtegra124-venice2.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
18 stdout-path = "serial0:115200n8";
29 vdd-supply = <&vdd_3v3_hdmi>;
30 pll-supply = <&vdd_hdmi_pll>;
31 hdmi-supply = <&vdd_5v0_hdmi>;
33 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
34 nvidia,hpd-gpio =
46 vdd-supply = <&vdd_3v3_panel>;
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/kernel/linux/linux-4.19/arch/arm64/boot/dts/nvidia/
Dtegra132-norrin.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
18 stdout-path = "serial0:115200n8";
30 vdd-supply = <&vdd_3v3_hdmi>;
31 pll-supply = <&vdd_hdmi_pll>;
32 hdmi-supply = <&vdd_5v0_hdmi>;
34 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
35 nvidia,hpd-gpio =
47 vdd-supply = <&vdd_3v3_panel>;
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/nvidia/
Dtegra132-norrin.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
18 stdout-path = "serial0:115200n8";
30 vdd-supply = <&vdd_3v3_hdmi>;
31 pll-supply = <&vdd_hdmi_pll>;
32 hdmi-supply = <&vdd_5v0_hdmi>;
34 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
35 nvidia,hpd-gpio =
42 avdd-io-hdmi-dp-supply = <&vdd_3v3_hdmi>;
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