| /kernel/linux/linux-5.10/arch/riscv/boot/dts/sifive/ |
| D | fu540-c000.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
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| /kernel/linux/linux-5.10/arch/arc/mm/ |
| D | tlb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * TLB Management (flush/create/diagnostics) for ARC700
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
8 * -Reintroduce duplicate PD fixup - some customer chips still have the issue
11 * -No need to flush_cache_page( ) for each call to update_mmu_cache()
13 * = page-fault thrice as fast (75 usec to 28 usec)
18 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
22 * -MMU v2/v3 BCRs decoded differently
23 * -Remove TLB_SIZE hardcoding as it's variable now: 256 or 512
24 * -tlb_entry_erase( ) can be void
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| /kernel/linux/linux-4.19/arch/arc/mm/ |
| D | tlb.c | 2 * TLB Management (flush/create/diagnostics) for ARC700
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
11 * -Reintroduce duplicate PD fixup - some customer chips still have the issue
14 * -No need to flush_cache_page( ) for each call to update_mmu_cache()
16 * = page-fault thrice as fast (75 usec to 28 usec)
21 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
25 * -MMU v2/v3 BCRs decoded differently
26 * -Remove TLB_SIZE hardcoding as it's variable now: 256 or 512
27 * -tlb_entry_erase( ) can be void
28 * -local_flush_tlb_range( ):
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V bindings for 'cpus' DT nodes
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 This document uses some terminology common to the RISC-V community
18 mandated by the RISC-V ISA: a PC and some registers. This
28 - items:
29 - enum:
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/riscv/ |
| D | cpus.txt | 2 RISC-V CPU Bindings
13 with updates for 32-bit and 64-bit RISC-V systems provided in this document.
19 This document uses some terminology common to the RISC-V community that is not
23 the RISC-V ISA: a PC and some registers. This terminology is designed to
33 The RISC-V architecture, in accordance with the Devicetree Specification,
37 - cpus node
45 - #address-cells
49 - #size-cells
54 - cpu node
60 - device_type
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| /kernel/linux/linux-4.19/arch/sh/kernel/cpu/sh5/ |
| D | probe.c | 4 * CPU Subtype Probing for SH-5.
7 * Copyright (C) 2003 - 2007 Paul Mundt
18 #include <asm/tlb.h>
26 * the WPC registers. On SH5-101 cut2, such a mapping would be in cpu_probe()
34 /* CPU.VCR aliased at CIR address on SH5-101 */ in cpu_probe()
40 * First, setup some sane values for the I-cache. in cpu_probe()
43 boot_cpu_data.icache.sets = 256; in cpu_probe()
47 boot_cpu_data.icache.way_size = boot_cpu_data.icache.sets * in cpu_probe()
53 * Next, setup some sane values for the D-cache. in cpu_probe()
55 * On the SH5, these are pretty consistent with the I-cache settings, in cpu_probe()
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| /kernel/linux/linux-4.19/arch/sh/mm/ |
| D | cache-sh5.c | 2 * arch/sh/mm/cache-sh5.c
7 * Copyright (C) 2003 - 2008 Paul Mundt
16 #include <asm/tlb.h>
25 /* Wired TLB entry for the D-cache */
73 /* Invalidate range of addresses [start,end] from the I-cache, where in sh64_icache_inv_kernel_range()
89 /* If we get called, we know that vma->vm_flags contains VM_EXEC. in sh64_icache_inv_user_page()
90 Also, eaddr is page-aligned. */ in sh64_icache_inv_user_page()
98 /* Check whether we can use the current ASID for the I-cache in sh64_icache_inv_user_page()
100 access_process_vm->flush_cache_page->here, (e.g. when reading from in sh64_icache_inv_user_page()
104 Also, note the risk that we might get pre-empted between the ASID in sh64_icache_inv_user_page()
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| /kernel/linux/linux-4.19/arch/powerpc/kernel/ |
| D | setup_64.c | 66 #include <asm/code-patching.h>
71 #include <asm/feature-fixups.h>
107 * If we boot via kdump on a non-primary thread, in setup_tlb_core_data()
109 * set up this TLB. in setup_tlb_core_data()
114 paca_ptrs[cpu]->tcd_ptr = &paca_ptrs[first]->tcd; in setup_tlb_core_data()
118 * or e6500 tablewalk mode, or else TLB handlers in setup_tlb_core_data()
134 /* Look for ibm,smt-enabled OF option */
161 smt_option = of_get_property(dn, "ibm,smt-enabled", in check_smt_enabled()
176 /* Look for smt-enabled= cmdline option */
182 early_param("smt-enabled", early_smt_enabled);
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| /kernel/linux/linux-4.19/arch/parisc/include/asm/ |
| D | ropes.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <asm/parisc-device.h>
8 /* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */
21 ** allocated and free'd/purged at a time might make this
33 unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */
34 unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */
38 unsigned long *res_hint; /* next avail IOVP - circular search */
85 unsigned int num_ioc; /* number of on-board IOC's */
95 static inline int IS_ASTRO(struct parisc_device *d) { in IS_ASTRO() argument
96 return d->id.hversion == ASTRO_RUNWAY_PORT; in IS_ASTRO()
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| /kernel/linux/linux-5.10/arch/parisc/include/asm/ |
| D | ropes.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <asm/parisc-device.h>
8 /* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */
21 ** allocated and free'd/purged at a time might make this
33 unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */
34 unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */
38 unsigned long *res_hint; /* next avail IOVP - circular search */
85 unsigned int num_ioc; /* number of on-board IOC's */
95 static inline int IS_ASTRO(struct parisc_device *d) { in IS_ASTRO() argument
96 return d->id.hversion == ASTRO_RUNWAY_PORT; in IS_ASTRO()
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| /kernel/linux/linux-5.10/arch/powerpc/kernel/ |
| D | setup_64.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
61 #include <asm/code-patching.h>
66 #include <asm/feature-fixups.h>
99 * If we boot via kdump on a non-primary thread, in setup_tlb_core_data()
101 * set up this TLB. in setup_tlb_core_data()
106 paca_ptrs[cpu]->tcd_ptr = &paca_ptrs[first]->tcd; in setup_tlb_core_data()
110 * or e6500 tablewalk mode, or else TLB handlers in setup_tlb_core_data()
126 /* Look for ibm,smt-enabled OF option */
153 smt_option = of_get_property(dn, "ibm,smt-enabled", in check_smt_enabled()
168 /* Look for smt-enabled= cmdline option */
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| /kernel/linux/linux-5.10/arch/mips/kvm/ |
| D | tlb.c | 6 * KVM/MIPS TLB handling, this file is part of the Linux host kernel so that
7 * TLB handlers run from KSEG0
26 #include <asm/tlb.h>
46 struct mm_struct *gpa_mm = &vcpu->kvm->arch.gpa_mm; in kvm_mips_get_root_asid()
57 struct mm_struct *kern_mm = &vcpu->arch.guest_kernel_mm; in kvm_mips_get_kernel_asid()
65 struct mm_struct *user_mm = &vcpu->arch.guest_user_mm; in kvm_mips_get_user_asid()
71 /* Structure defining an tlb entry data set. */
90 struct mips_coproc *cop0 = vcpu->arch.cop0; in kvm_mips_dump_guest_tlbs()
91 struct kvm_mips_tlb tlb; in kvm_mips_dump_guest_tlbs() local
98 tlb = vcpu->arch.guest_tlb[i]; in kvm_mips_dump_guest_tlbs()
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| /kernel/linux/linux-4.19/arch/mips/kvm/ |
| D | tlb.c | 6 * KVM/MIPS TLB handling, this file is part of the Linux host kernel so that
7 * TLB handlers run from KSEG0
26 #include <asm/tlb.h>
46 struct mm_struct *gpa_mm = &vcpu->kvm->arch.gpa_mm; in kvm_mips_get_root_asid()
57 struct mm_struct *kern_mm = &vcpu->arch.guest_kernel_mm; in kvm_mips_get_kernel_asid()
65 struct mm_struct *user_mm = &vcpu->arch.guest_user_mm; in kvm_mips_get_user_asid()
71 /* Structure defining an tlb entry data set. */
90 struct mips_coproc *cop0 = vcpu->arch.cop0; in kvm_mips_dump_guest_tlbs()
91 struct kvm_mips_tlb tlb; in kvm_mips_dump_guest_tlbs() local
98 tlb = vcpu->arch.guest_tlb[i]; in kvm_mips_dump_guest_tlbs()
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| /kernel/linux/linux-5.10/arch/openrisc/mm/ |
| D | tlb.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * OpenRISC tlb.c
11 * Copyright (C) 2010-2011 Julius Baxter <julius.baxter@orsoc.se>
12 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
29 #define NO_CONTEXT -1
35 #define DTLB_OFFSET(addr) (((addr) >> PAGE_SHIFT) & (NUM_DTLB_SETS-1))
36 #define ITLB_OFFSET(addr) (((addr) >> PAGE_SHIFT) & (NUM_ITLB_SETS-1))
38 * Invalidate all TLB entries.
51 /* Determine number of sets for IMMU. */ in local_flush_tlb_all()
52 /* FIXME: Assumption is I & D nsets equal. */ in local_flush_tlb_all()
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| /kernel/linux/linux-4.19/arch/openrisc/mm/ |
| D | tlb.c | 2 * OpenRISC tlb.c
10 * Copyright (C) 2010-2011 Julius Baxter <julius.baxter@orsoc.se>
11 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
35 #define NO_CONTEXT -1
41 #define DTLB_OFFSET(addr) (((addr) >> PAGE_SHIFT) & (NUM_DTLB_SETS-1))
42 #define ITLB_OFFSET(addr) (((addr) >> PAGE_SHIFT) & (NUM_ITLB_SETS-1))
44 * Invalidate all TLB entries.
57 /* Determine number of sets for IMMU. */ in local_flush_tlb_all()
58 /* FIXME: Assumption is I & D nsets equal. */ in local_flush_tlb_all()
74 * the data or instruction TLB that should be flushed... that would take more
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| /kernel/linux/linux-5.10/arch/mips/mm/ |
| D | c-octeon.c | 6 * Copyright (C) 2005-2007 Cavium Networks
20 #include <asm/cpu-features.h>
21 #include <asm/cpu-type.h>
34 * Octeon automatically flushes the dcache on tlb changes, so
50 * Flush local I-cache for the specified range.
83 mask = *mm_cpumask(vma->vm_mm); in octeon_flush_icache_all_cores()
139 if (vma->vm_flags & VM_EXEC) in octeon_flush_cache_range()
154 if (vma->vm_flags & VM_EXEC) in octeon_flush_cache_page()
179 c->icache.linesz = 2 << ((config1 >> 19) & 7); in probe_octeon()
180 c->icache.sets = 64 << ((config1 >> 22) & 7); in probe_octeon()
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| /kernel/linux/linux-5.10/Documentation/x86/ |
| D | pti.rst | 1 .. SPDX-License-Identifier: GPL-2.0
27 This approach helps to ensure that side-channel attacks leveraging
30 Once enabled at compile-time, it can be disabled at boot with the
31 'nopti' or 'pti=' kernel parameters (see kernel-parameters.txt).
36 When PTI is enabled, the kernel manages two sets of page tables.
43 that any missed kernel->user CR3 switch will immediately crash
49 each CPU's copy of the area a compile-time-fixed virtual address.
65 Protection against side-channel attacks is important. But,
70 a. Each process now needs an order-1 PGD instead of order-0.
86 non-PTI SYSCALL entry code, so requires mapping fewer
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| D | sva.rst | 1 .. SPDX-License-Identifier: GPL-2.0
19 application page-faults. For more information please refer to the PCIe
25 mmu_notifier() support to keep the device TLB cache and the CPU cache in
34 Unlike Single Root I/O Virtualization (SR-IOV), Scalable IOV (SIOV) permits
40 ID (PASID), which is a 20-bit number defined by the PCIe SIG.
43 IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe
55 ENQCMD works with non-posted semantics and carries a status back if the
67 A new thread-scoped MSR (IA32_PASID) provides the connection between
69 accesses an SVA-capable device, this MSR is initialized with a newly
70 allocated PASID. The driver for the device calls an IOMMU-specific API
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| /kernel/linux/linux-4.19/Documentation/x86/ |
| D | pti.txt | 21 This approach helps to ensure that side-channel attacks leveraging
24 Once enabled at compile-time, it can be disabled at boot with the
25 'nopti' or 'pti=' kernel parameters (see kernel-parameters.txt).
30 When PTI is enabled, the kernel manages two sets of page tables.
37 that any missed kernel->user CR3 switch will immediately crash
43 each CPU's copy of the area a compile-time-fixed virtual address.
59 Protection against side-channel attacks is important. But,
63 a. Each process now needs an order-1 PGD instead of order-0.
78 non-PTI SYSCALL entry code, so requires mapping fewer
83 feature of the MMU allows different processes to share TLB
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| /kernel/linux/linux-4.19/arch/mips/mm/ |
| D | c-octeon.c | 6 * Copyright (C) 2005-2007 Cavium Networks
20 #include <asm/cpu-features.h>
21 #include <asm/cpu-type.h>
35 * Octeon automatically flushes the dcache on tlb changes, so
51 * Flush local I-cache for the specified range.
84 mask = *mm_cpumask(vma->vm_mm); in octeon_flush_icache_all_cores()
140 down_read(¤t->mm->mmap_sem); in octeon_flush_cache_sigtramp()
141 vma = find_vma(current->mm, addr); in octeon_flush_cache_sigtramp()
143 up_read(¤t->mm->mmap_sem); in octeon_flush_cache_sigtramp()
157 if (vma->vm_flags & VM_EXEC) in octeon_flush_cache_range()
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| /kernel/linux/linux-5.10/include/asm-generic/ |
| D | tlb.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* include/asm-generic/tlb.h
4 * Generic TLB shootdown code
32 * Generic MMU-gather implementation.
35 * correct and efficient ordering of freeing pages and TLB invalidations.
40 * 2) TLB invalidate page
49 * - tlb_gather_mmu() / tlb_finish_mmu(); start and finish a mmu_gather
51 * Finish in particular will issue a (final) TLB invalidate and free
54 * - tlb_start_vma() / tlb_end_vma(); marks the start / end of a VMA
59 * - tlb_remove_table()
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| /kernel/linux/linux-4.19/arch/nds32/kernel/ |
| D | setup.c | 1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2005-2017 Andes Technology Corporation
11 #include <linux/dma-mapping.h>
16 #include <asm/proc-fns.h>
99 pr_info("CPU%d Features: %s\n", cpu, str); in dump_cpu_info()
103 L1_cache_info[ICACHE].sets = CACHE_SET(ICACHE); in dump_cpu_info()
106 L1_cache_info[ICACHE].sets / 1024; in dump_cpu_info()
108 L1_cache_info[ICACHE].sets, L1_cache_info[ICACHE].ways, in dump_cpu_info()
112 L1_cache_info[DCACHE].sets = CACHE_SET(DCACHE); in dump_cpu_info()
115 L1_cache_info[DCACHE].sets / 1024; in dump_cpu_info()
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| /kernel/linux/linux-5.10/drivers/parisc/ |
| D | ccio-dma.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 ** ccio-dma.c:
4 ** DMA management routines for first generation cache-coherent machines.
9 ** (c) Copyright 2000 Hewlett-Packard Company
15 ** the I/O MMU - basically what x86 does.
17 ** Philipp Rumpf has a "Real Mode" driver for PCX-W machines at:
18 ** CVSROOT=:pserver:anonymous@198.186.203.37:/cvsroot/linux-parisc
19 ** cvs -z3 co linux/arch/parisc/kernel/dma-rm.c
21 ** I've rewritten his code to work under TPG's tree. See ccio-rm-dma.c.
24 ** o outbound DMA is slower - U2 won't prefetch data (GSC+ XQL signal).
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| /kernel/linux/linux-4.19/drivers/parisc/ |
| D | ccio-dma.c | 2 ** ccio-dma.c:
3 ** DMA management routines for first generation cache-coherent machines.
8 ** (c) Copyright 2000 Hewlett-Packard Company
18 ** the I/O MMU - basically what x86 does.
20 ** Philipp Rumpf has a "Real Mode" driver for PCX-W machines at:
21 ** CVSROOT=:pserver:anonymous@198.186.203.37:/cvsroot/linux-parisc
22 ** cvs -z3 co linux/arch/parisc/kernel/dma-rm.c
24 ** I've rewritten his code to work under TPG's tree. See ccio-rm-dma.c.
27 ** o outbound DMA is slower - U2 won't prefetch data (GSC+ XQL signal).
28 ** o Inbound DMA less efficient - U2 can't use DMA_FAST attribute.
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| /kernel/linux/linux-5.10/arch/nds32/kernel/ |
| D | setup.c | 1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2005-2017 Andes Technology Corporation
10 #include <linux/dma-mapping.h>
15 #include <asm/proc-fns.h>
102 pr_info("CPU%d Features: %s\n", cpu, str); in dump_cpu_info()
106 L1_cache_info[ICACHE].sets = CACHE_SET(ICACHE); in dump_cpu_info()
109 L1_cache_info[ICACHE].sets / 1024; in dump_cpu_info()
111 L1_cache_info[ICACHE].sets, L1_cache_info[ICACHE].ways, in dump_cpu_info()
115 L1_cache_info[DCACHE].sets = CACHE_SET(DCACHE); in dump_cpu_info()
118 L1_cache_info[DCACHE].sets / 1024; in dump_cpu_info()
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