| /kernel/linux/linux-5.10/arch/riscv/boot/dts/sifive/ |
| D | fu540-c000.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
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| /kernel/linux/linux-4.19/arch/parisc/kernel/ |
| D | cache.c | 6 * Copyright (C) 1999-2006 Helge Deller <deller@gmx.de> (07-13-1999)
10 * Cache and TLB management
44 * by software. We put a spinlock around all TLB flushes to
92 test_bit(PG_dcache_dirty, &page->flags)) { in update_mmu_cache()
94 clear_bit(PG_dcache_dirty, &page->flags); in update_mmu_cache()
104 seq_printf(m, "I-cache\t\t: %ld KB\n", in show_cache_info()
107 snprintf(buf, 32, "%lu-way associative", cache_info.dc_loop); in show_cache_info()
108 seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %s)\n", in show_cache_info()
111 (cache_info.dc_conf.cc_sh ? ", shared I/D":""), in show_cache_info()
116 cache_info.dt_conf.tc_sh ? " - shared with ITLB":"" in show_cache_info()
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| /kernel/linux/linux-5.10/arch/parisc/kernel/ |
| D | cache.c | 6 * Copyright (C) 1999-2006 Helge Deller <deller@gmx.de> (07-13-1999)
10 * Cache and TLB management
44 * by software. We need a spinlock around all TLB flushes to ensure
99 test_bit(PG_dcache_dirty, &page->flags)) { in update_mmu_cache()
101 clear_bit(PG_dcache_dirty, &page->flags); in update_mmu_cache()
111 seq_printf(m, "I-cache\t\t: %ld KB\n", in show_cache_info()
114 snprintf(buf, 32, "%lu-way associative", cache_info.dc_loop); in show_cache_info()
115 seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %s)\n", in show_cache_info()
118 (cache_info.dc_conf.cc_sh ? ", shared I/D":""), in show_cache_info()
123 cache_info.dt_conf.tc_sh ? " - shared with ITLB":"" in show_cache_info()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V bindings for 'cpus' DT nodes
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 This document uses some terminology common to the RISC-V community
18 mandated by the RISC-V ISA: a PC and some registers. This
28 - items:
29 - enum:
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| /kernel/linux/linux-4.19/Documentation/core-api/ |
| D | cachetlb.rst | 2 Cache and TLB Flushing Under Linux
7 This document describes the cache/tlb flushing interfaces called
17 thinking SMP cache/tlb flushing must be so inefficient, this is in
23 First, the TLB flushing interfaces, since they are the simplest. The
24 "TLB" is abstracted under Linux as something the cpu uses to cache
25 virtual-->physical address translations obtained from the software
27 possible for stale translations to exist in this "TLB" cache.
44 the TLB. After running, this interface must make sure that
47 there will be no entries in the TLB for 'mm'.
57 address translations from the TLB. After running, this
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| /kernel/linux/linux-5.10/arch/arc/mm/ |
| D | tlb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * TLB Management (flush/create/diagnostics) for ARC700
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
8 * -Reintroduce duplicate PD fixup - some customer chips still have the issue
11 * -No need to flush_cache_page( ) for each call to update_mmu_cache()
13 * = page-fault thrice as fast (75 usec to 28 usec)
18 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
22 * -MMU v2/v3 BCRs decoded differently
23 * -Remove TLB_SIZE hardcoding as it's variable now: 256 or 512
24 * -tlb_entry_erase( ) can be void
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| D | tlbex.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * TLB Exception Handling for ARC
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
8 * -MMU v1: moved out legacy code into a seperate file
9 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
13 * -For MMU V2, we need not do heuristics at the time of commiting a D-TLB
14 * entry, so that it doesn't knock out it's I-TLB entry
15 * -Some more fine tuning:
19 * -Practically rewrote the I/D TLB Miss handlers
26 * -Passing ECR (Exception Cause REG) to do_page_fault( ) for printing
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/riscv/ |
| D | cpus.txt | 2 RISC-V CPU Bindings
13 with updates for 32-bit and 64-bit RISC-V systems provided in this document.
19 This document uses some terminology common to the RISC-V community that is not
23 the RISC-V ISA: a PC and some registers. This terminology is designed to
33 The RISC-V architecture, in accordance with the Devicetree Specification,
37 - cpus node
45 - #address-cells
49 - #size-cells
54 - cpu node
60 - device_type
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| /kernel/linux/linux-5.10/Documentation/core-api/ |
| D | cachetlb.rst | 2 Cache and TLB Flushing Under Linux
7 This document describes the cache/tlb flushing interfaces called
17 thinking SMP cache/tlb flushing must be so inefficient, this is in
23 First, the TLB flushing interfaces, since they are the simplest. The
24 "TLB" is abstracted under Linux as something the cpu uses to cache
25 virtual-->physical address translations obtained from the software
27 possible for stale translations to exist in this "TLB" cache.
44 the TLB. After running, this interface must make sure that
47 there will be no entries in the TLB for 'mm'.
57 address translations from the TLB. After running, this
[all …]
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| /kernel/linux/linux-4.19/arch/arc/mm/ |
| D | tlb.c | 2 * TLB Management (flush/create/diagnostics) for ARC700
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
11 * -Reintroduce duplicate PD fixup - some customer chips still have the issue
14 * -No need to flush_cache_page( ) for each call to update_mmu_cache()
16 * = page-fault thrice as fast (75 usec to 28 usec)
21 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
25 * -MMU v2/v3 BCRs decoded differently
26 * -Remove TLB_SIZE hardcoding as it's variable now: 256 or 512
27 * -tlb_entry_erase( ) can be void
28 * -local_flush_tlb_range( ):
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| D | tlbex.S | 2 * TLB Exception Handling for ARC
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
11 * -MMU v1: moved out legacy code into a seperate file
12 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
16 * -For MMU V2, we need not do heuristics at the time of commiting a D-TLB
17 * entry, so that it doesn't knock out it's I-TLB entry
18 * -Some more fine tuning:
22 * -Practically rewrote the I/D TLB Miss handlers
29 * -Passing ECR (Exception Cause REG) to do_page_fault( ) for printing
33 * -Added Debug Code to check if sw-ASID == hw-ASID
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| /kernel/linux/linux-5.10/include/asm-generic/ |
| D | tlb.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* include/asm-generic/tlb.h
4 * Generic TLB shootdown code
32 * Generic MMU-gather implementation.
35 * correct and efficient ordering of freeing pages and TLB invalidations.
40 * 2) TLB invalidate page
49 * - tlb_gather_mmu() / tlb_finish_mmu(); start and finish a mmu_gather
51 * Finish in particular will issue a (final) TLB invalidate and free
54 * - tlb_start_vma() / tlb_end_vma(); marks the start / end of a VMA
59 * - tlb_remove_table()
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| /kernel/linux/linux-4.19/arch/parisc/include/uapi/asm/ |
| D | pdc.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
14 #define PDC_BAD_PROC -1 /* Called non-existent procedure*/
15 #define PDC_BAD_OPTION -2 /* Called with non-existent option */
16 #define PDC_ERROR -3 /* Call could not complete without an error */
17 #define PDC_NE_MOD -5 /* Module not found */
18 #define PDC_NE_CELL_MOD -7 /* Cell module not found */
19 #define PDC_NE_BOOTDEV -9 /* Cannot locate a console device or boot device */
20 #define PDC_INVALID_ARG -10 /* Called with an invalid argument */
21 #define PDC_BUS_POW_WARN -12 /* Call could not complete in allowed power budget */
22 #define PDC_NOT_NARROW -17 /* Narrow mode not supported */
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| /kernel/linux/linux-5.10/arch/parisc/include/uapi/asm/ |
| D | pdc.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
14 #define PDC_BAD_PROC -1 /* Called non-existent procedure*/
15 #define PDC_BAD_OPTION -2 /* Called with non-existent option */
16 #define PDC_ERROR -3 /* Call could not complete without an error */
17 #define PDC_NE_MOD -5 /* Module not found */
18 #define PDC_NE_CELL_MOD -7 /* Cell module not found */
19 #define PDC_NE_BOOTDEV -9 /* Cannot locate a console device or boot device */
20 #define PDC_INVALID_ARG -10 /* Called with an invalid argument */
21 #define PDC_BUS_POW_WARN -12 /* Call could not complete in allowed power budget */
22 #define PDC_NOT_NARROW -17 /* Narrow mode not supported */
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| /kernel/linux/linux-5.10/drivers/parisc/ |
| D | ccio-dma.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 ** ccio-dma.c:
4 ** DMA management routines for first generation cache-coherent machines.
9 ** (c) Copyright 2000 Hewlett-Packard Company
15 ** the I/O MMU - basically what x86 does.
17 ** Philipp Rumpf has a "Real Mode" driver for PCX-W machines at:
18 ** CVSROOT=:pserver:anonymous@198.186.203.37:/cvsroot/linux-parisc
19 ** cvs -z3 co linux/arch/parisc/kernel/dma-rm.c
21 ** I've rewritten his code to work under TPG's tree. See ccio-rm-dma.c.
24 ** o outbound DMA is slower - U2 won't prefetch data (GSC+ XQL signal).
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| /kernel/linux/linux-4.19/drivers/parisc/ |
| D | ccio-dma.c | 2 ** ccio-dma.c:
3 ** DMA management routines for first generation cache-coherent machines.
8 ** (c) Copyright 2000 Hewlett-Packard Company
18 ** the I/O MMU - basically what x86 does.
20 ** Philipp Rumpf has a "Real Mode" driver for PCX-W machines at:
21 ** CVSROOT=:pserver:anonymous@198.186.203.37:/cvsroot/linux-parisc
22 ** cvs -z3 co linux/arch/parisc/kernel/dma-rm.c
24 ** I've rewritten his code to work under TPG's tree. See ccio-rm-dma.c.
27 ** o outbound DMA is slower - U2 won't prefetch data (GSC+ XQL signal).
28 ** o Inbound DMA less efficient - U2 can't use DMA_FAST attribute.
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| /kernel/linux/linux-5.10/arch/powerpc/mm/nohash/ |
| D | 44x.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * -- paulus
11 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
27 #include <asm/code-patching.h>
31 /* Used by the 44x TLB replacement exception handler.
35 unsigned int tlb_44x_hwater = PPC44x_TLB_SIZE - 1 - PPC44x_EARLY_TLBS;
42 /* The TLB miss handlers hard codes the watermark in a cmpli in ppc44x_update_tlb_hwater()
45 * in the 2 TLB miss handlers when updating the value in ppc44x_update_tlb_hwater()
52 * "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 44x type MMU
56 unsigned int entry = tlb_44x_hwater--; in ppc44x_pin_tlb()
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| /kernel/linux/linux-5.10/arch/sparc/kernel/ |
| D | tsb.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
17 /* Invoked from TLB miss handler, we are in the
23 * %g3: FAULT_CODE_{D,I}TLB
46 * %g1 -- PAGE_SIZE TSB entry address
47 * %g3 -- FAULT_CODE_{D,I}TLB
48 * %g4 -- missing virtual address
49 * %g6 -- TAG TARGET (vaddr >> 22)
67 cmp %g5, -1
106 * %g1 -- TSB entry address
107 * %g3 -- FAULT_CODE_{D,I}TLB
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| /kernel/linux/linux-4.19/arch/sparc/kernel/ |
| D | tsb.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
17 /* Invoked from TLB miss handler, we are in the
23 * %g3: FAULT_CODE_{D,I}TLB
46 * %g1 -- PAGE_SIZE TSB entry address
47 * %g3 -- FAULT_CODE_{D,I}TLB
48 * %g4 -- missing virtual address
49 * %g6 -- TAG TARGET (vaddr >> 22)
67 cmp %g5, -1
106 * %g1 -- TSB entry address
107 * %g3 -- FAULT_CODE_{D,I}TLB
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| /kernel/linux/linux-4.19/arch/powerpc/mm/ |
| D | 44x_mmu.c | 7 * -- paulus
10 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
35 /* Used by the 44x TLB replacement exception handler.
39 unsigned int tlb_44x_hwater = PPC44x_TLB_SIZE - 1 - PPC44x_EARLY_TLBS;
49 /* The TLB miss handlers hard codes the watermark in a cmpli in ppc44x_update_tlb_hwater()
52 * in the 2 TLB miss handlers when updating the value in ppc44x_update_tlb_hwater()
65 * "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 44x type MMU
69 unsigned int entry = tlb_44x_hwater--; in ppc44x_pin_tlb()
106 return -1; in ppc47x_find_free_bolted()
135 * "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 47x type MMU
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| /kernel/linux/linux-5.10/arch/arc/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
98 source "arch/arc/plat-tb10x/Kconfig"
99 source "arch/arc/plat-axs10x/Kconfig"
100 source "arch/arc/plat-hsdk/Kconfig"
118 ISA for the Next Generation ARC-HS cores
143 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
144 Shared Address Spaces (for sharing TLB entries in MMU)
145 -Caches: New Prog Model, Region Flush
146 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
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| /kernel/linux/linux-4.19/arch/arc/ |
| D | Kconfig | 2 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
105 source "arch/arc/plat-tb10x/Kconfig"
106 source "arch/arc/plat-axs10x/Kconfig"
108 source "arch/arc/plat-eznps/Kconfig"
109 source "arch/arc/plat-hsdk/Kconfig"
127 ISA for the Next Generation ARC-HS cores
152 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
153 Shared Address Spaces (for sharing TLB entries in MMU)
154 -Caches: New Prog Model, Region Flush
155 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
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| /kernel/linux/linux-4.19/include/asm-generic/ |
| D | tlb.h | 1 /* include/asm-generic/tlb.h
3 * Generic TLB shootdown code
29 * gup_fast() and other software pagetable walkers do a lockless page-table
36 * IRQs delays the completion of the TLB flush we can never observe an already
59 ((PAGE_SIZE - sizeof(struct mmu_table_batch)) / sizeof(void *))
61 extern void tlb_table_flush(struct mmu_gather *tlb);
62 extern void tlb_remove_table(struct mmu_gather *tlb, void *table);
68 * to work on, then just handle a few from the on-stack structure.
80 ((PAGE_SIZE - sizeof(struct mmu_gather_batch)) / sizeof(void *))
84 * lockups for non-preemptible kernels on huge machines when a lot of memory
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| /kernel/linux/linux-4.19/arch/nds32/kernel/ |
| D | head.S | 1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2005-2017 Andes Technology Corporation
7 #include <asm/asm-offsets.h>
20 .equ swapper_pg_dir, TEXTADDR - 0x4000
28 setgie.d ! Disable interrupt
31 * Disable I/D-cache and enable it at a proper time
54 li $p0, (PAGE_OFFSET - PHYS_OFFSET)
56 tlbop FlushAll ! invalidate TLB\n"
70 /* set NTC cacheability, mutliple page size in use */
94 /* set page size and size of kernel image */
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| /kernel/linux/linux-5.10/arch/ia64/include/asm/ |
| D | mmu_context.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (C) 1998-2002 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
12 * numbers are used to reduce or eliminate the need to perform TLB flushes
13 * due to context switches. Context numbers are implemented using ia-64
14 * region ids. Since the IA-64 TLB does not consider the region number when
15 * performing a TLB lookup, we need to assign a unique region id to each
20 #define IA64_REGION_ID_KERNEL 0 /* the kernel's region id (tlb.c depends on this being 0) */
34 #include <asm-generic/mm_hooks.h>
42 unsigned long *bitmap; /* bitmap size is max_ctx+1 */
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