| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/ |
| D | uncore-ddrc.json | 5 "BriefDescription": "DDRC total write operations",
6 "PublicDescription": "DDRC total write operations",
7 "Unit": "hisi_sccl,ddrc"
12 "BriefDescription": "DDRC total read operations",
13 "PublicDescription": "DDRC total read operations",
14 "Unit": "hisi_sccl,ddrc"
19 "BriefDescription": "DDRC write commands",
20 "PublicDescription": "DDRC write commands",
21 "Unit": "hisi_sccl,ddrc"
26 "BriefDescription": "DDRC read commands",
[all …]
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| D | uncore-hha.json | 33 "BriefDescription": "The number of read operations sent by HHA to DDRC which size is 64 bytes",
34 "PublicDescription": "The number of read operations sent by HHA to DDRC which size is 64bytes",
40 … "BriefDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes",
41 … "PublicDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes",
47 … "BriefDescription": "The number of read operations sent by HHA to DDRC which size is 128 bytes",
48 … "PublicDescription": "The number of read operations sent by HHA to DDRC which size is 128 bytes",
54 … "BriefDescription": "The number of write operations sent by HHA to DDRC which size is 128 bytes",
55 … "PublicDescription": "The number of write operations sent by HHA to DDRC which size is 128 bytes",
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/fsl/ |
| D | imx8m-ddrc.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml#
13 The DDRC block is integrated in i.MX8M for interfacing with DDR based
20 The Linux driver for the DDRC doesn't even map registers (they're included
28 - fsl,imx8mn-ddrc
29 - fsl,imx8mm-ddrc
30 - fsl,imx8mq-ddrc
31 - const: fsl,imx8m-ddrc
36 Base address and size of DDRC CTL area.
37 This is not currently mapped by the imx8m-ddrc driver.
63 ddrc: memory-controller@3d400000 {
[all …]
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| /kernel/linux/linux-4.19/drivers/perf/hisilicon/ |
| D | hisi_uncore_ddrc_pmu.c | 2 * HiSilicon SoC DDRC uncore Hardware event counters support
25 /* DDRC register definition */
40 /* DDRC has 8-counters */
45 * For DDRC PMU, there are eight-events and every event has been mapped
59 * In DDRC there are no programmable counter, the count
96 * For DDRC PMU, event has been mapped to fixed-purpose counter by hardware,
151 /* For DDRC PMU, we use event code as counter index */ in hisi_ddrc_pmu_get_event_idx()
224 dev_err(&pdev->dev, "DDRC PMU get irq fail; irq:%d\n", irq); in hisi_ddrc_pmu_init_irq()
254 * Use the SCCL_ID and DDRC channel ID to identify the in hisi_ddrc_pmu_init_data()
255 * DDRC PMU, while SCCL_ID is in MPIDR[aff2]. in hisi_ddrc_pmu_init_data()
[all …]
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| /kernel/linux/linux-5.10/drivers/perf/hisilicon/ |
| D | hisi_uncore_ddrc_pmu.c | 3 * HiSilicon SoC DDRC uncore Hardware event counters support
22 /* DDRC register definition */
37 /* DDRC has 8-counters */
42 * For DDRC PMU, there are eight-events and every event has been mapped
56 * In DDRC there are no programmable counter, the count
93 * For DDRC PMU, event has been mapped to fixed-purpose counter by hardware,
148 /* For DDRC PMU, we use event code as counter index */ in hisi_ddrc_pmu_get_event_idx()
247 * Use the SCCL_ID and DDRC channel ID to identify the in hisi_ddrc_pmu_init_data()
248 * DDRC PMU, while SCCL_ID is in MPIDR[aff2]. in hisi_ddrc_pmu_init_data()
252 dev_err(&pdev->dev, "Can not read ddrc channel-id!\n"); in hisi_ddrc_pmu_init_data()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | synopsys.txt | 14 - 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller
15 - 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller
18 Required properties for "xlnx,zynqmp-ddrc-2.40a":
23 compatible = "xlnx,zynq-ddrc-a05";
28 compatible = "xlnx,zynqmp-ddrc-2.40a";
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interconnect/ |
| D | fsl,imx8m-noc.yaml | 50 fsl,ddrc:
78 fsl,ddrc = <&ddrc>;
93 ddrc: memory-controller@3d400000 {
94 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
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| /kernel/linux/linux-4.19/Documentation/perf/ |
| D | hisi-pmu.txt | 4 such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are
17 HHA and DDRC etc. The available events and configuration options shall
19 /sys/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>/, or
20 /sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>.
23 Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/test/test_cpu/ |
| D | uncore.json | 5 "BriefDescription": "DDRC write commands",
6 "PublicDescription": "DDRC write commands",
7 "Unit": "hisi_sccl,ddrc"
|
| /kernel/linux/linux-5.10/Documentation/admin-guide/perf/ |
| D | hisi-pmu.rst | 6 such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are
20 HHA and DDRC etc. The available events and configuration options shall
23 /sys/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>/, or
24 /sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>.
27 Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
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| /kernel/linux/linux-5.10/arch/arm/mach-zynq/ |
| D | pm.c | 58 ddrc_base = zynq_pm_ioremap("xlnx,zynq-ddrc-a05"); in zynq_pm_late_init()
60 pr_warn("%s: Unable to map DDRC IO memory.\n", __func__); in zynq_pm_late_init()
63 * Enable DDRC clock stop feature. The HW takes care of in zynq_pm_late_init()
|
| /kernel/linux/linux-4.19/arch/arm/mach-zynq/ |
| D | pm.c | 70 ddrc_base = zynq_pm_ioremap("xlnx,zynq-ddrc-a05"); in zynq_pm_late_init()
72 pr_warn("%s: Unable to map DDRC IO memory.\n", __func__); in zynq_pm_late_init()
75 * Enable DDRC clock stop feature. The HW takes care of in zynq_pm_late_init()
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/memory-controllers/ |
| D | synopsys.txt | 8 - compatible: Should be 'xlnx,zynq-ddrc-a05'
13 compatible = "xlnx,zynq-ddrc-a05";
|
| /kernel/linux/linux-5.10/drivers/devfreq/ |
| D | imx8m-ddrc.c | 262 dev_err(dev, "ddrc failed freq switch to %lu from %lu: error %d. now at %lu\n", in imx8m_ddrc_target()
265 dev_err(dev, "ddrc failed freq update to %lu from %lu, now at %lu\n", in imx8m_ddrc_target()
268 dev_dbg(dev, "ddrc freq set to %lu (was %lu)\n", in imx8m_ddrc_target()
455 { .compatible = "fsl,imx8m-ddrc", },
463 .name = "imx8m-ddrc-devfreq",
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| D | Makefile | 13 obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
|
| /kernel/linux/linux-5.10/tools/perf/tests/ |
| D | pmu-events.c | 93 .desc = "DDRC write commands. Unit: hisi_sccl,ddrc ",
95 .long_desc = "DDRC write commands",
96 .pmu = "hisi_sccl,ddrc",
99 .alias_long_desc = "DDRC write commands",
|
| /kernel/linux/linux-4.19/arch/mips/pmcs-msp71xx/ |
| D | msp_setup.c | 68 /* Put the DDRC into self-refresh mode */ in msp7120_reset()
80 /* Wait a bit for the DDRC to settle */ in msp7120_reset()
|
| /kernel/linux/linux-4.19/drivers/perf/ |
| D | Kconfig | 69 unit (PMU), such as: L3C, HHA and DDRC.
|
| /kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/ |
| D | imx8mm-evk.dts | 20 &ddrc {
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| /kernel/linux/linux-5.10/drivers/interconnect/imx/ |
| D | imx8mn.c | 17 .phandle_name = "fsl,ddrc",
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| D | imx8mm.c | 20 .phandle_name = "fsl,ddrc",
|
| D | imx8mq.c | 18 .phandle_name = "fsl,ddrc",
|
| /kernel/linux/linux-4.19/arch/arm/mach-at91/ |
| D | pm_suspend.S | 377 /* Active DDRC self-refresh mode */
398 /* Active DDRC self-refresh mode */
|
| /kernel/linux/linux-5.10/drivers/edac/ |
| D | synopsys_edac.c | 202 /* DDRC Software control register */
205 /* DDRC ECC CE & UE poison mask */
209 /* DDRC Device config masks */
895 .compatible = "xlnx,zynq-ddrc-a05",
899 .compatible = "xlnx,zynqmp-ddrc-2.40a",
1355 "xlnx,zynqmp-ddrc-2.40a")) in mc_probe()
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| /kernel/linux/linux-4.19/arch/mips/include/asm/mach-rc32434/ |
| D | ddr.h | 40 u32 ddrc; member
|