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3 menu "Clock driver for ARM Reference designs"8 bool "Clock driver for ARM Reference designs ICST"11 Supports clocking on ARM Reference designs:
2 tristate "Audio support for Analog Devices reference designs"5 Audio support for various reference designs by Analog Devices.
3 tristate "Audio support for Analog Devices reference designs"6 Audio support for various reference designs by Analog Devices.
5 bool "Clock driver for ARM Reference designs"11 Supports clocking on ARM Reference designs:
17 and similar designs that utilize a hardware reset circuit. To18 support different CW1200 SDIO designs you will need to override
18 and similar designs that utilize a hardware reset circuit. To19 support different CW1200 SDIO designs you will need to override
4 common properties between various SOC designs. It thus enables us to use the5 same provider for several SOC designs.
14 of common properties between various SOC designs. It thus enables us to use15 the same provider for several SOC designs.
3 * Copyright (C) 2017 Sigma Designs88 MODULE_AUTHOR("Sigma Designs");
74 the Xilinx ML3xx and ML4xx reference designs using the powerpc77 Most Virtex designs should use this unless it needs to do some
2 * Copyright (C) 2017 Sigma Designs91 MODULE_AUTHOR("Sigma Designs");
109 Hisilicon designs this controller as one of the system controllers,130 Hisilicon designs this system controller to control the power always150 Hisilicon designs this system controller to control the multimedia170 Hisilicon designs this system controller to control the power management
13 The ARM RealView series of reference designs were built to explore the ARM23 as a generic platform to test different FPGA designs, and has
51 and read <file:Documentation/sound/designs/oss-emulation.rst>.64 here and read <file:Documentation/sound/designs/oss-emulation.rst>.
52 and read <file:Documentation/sound/designs/oss-emulation.rst>.65 here and read <file:Documentation/sound/designs/oss-emulation.rst>.
90 For CPU domain, the different SoC designs have different power management101 - Some designs will power down an entire cluster if all CPUs on the cluster104 respected in these cases, so these designs do not support debug over
92 For CPU domain, the different SoC designs have different power management103 - Some designs will power down an entire cluster if all CPUs on the cluster106 respected in these cases, so these designs do not support debug over
3 bool "Sigma Designs Tango4 (SMP87xx)"
1 Designs and Implementations
1 Sigma Designs SMP86xx/SMP87xx watchdog
7 platform bus to obtain component resources. The designs used to test this32 SGDMA support is included for existing designs and reference in case a34 new designs should not use the SGDMA.
9 designs/index