| /kernel/linux/linux-5.10/arch/arm/mach-omap2/ |
| D | sleep24xx.S | 31 * R0 : DLL ctrl value pre-Sleep
36 * when we get called, but the DLL probably isn't. We will wait a bit more in
37 * case the DPLL isn't quite there yet. The code will wait on DLL for DDR even
48 * The DLL load value is not kept in RETENTION or OFF. It needs to be restored
60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
76 strne r0, [r1] @ rewrite DLLA to force DLL reload
78 strne r0, [r1] @ rewrite DLLB to force DLL reload
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| D | sram242x.S | 45 /* dll lock mode */
52 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
55 bl i_dll_wait @ wait for dll to lock
57 /* get dll value */
84 /* ensure the DLL has relocked */
86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
172 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
173 bne freq_out @ leave if SDR, no DLL function
175 /* With DDR, we need to take care of the DLL for the frequency change */
180 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
[all …]
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| D | sram243x.S | 45 /* dll lock mode */
52 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
55 bl i_dll_wait @ wait for dll to lock
57 /* get dll value */
84 /* ensure the DLL has relocked */
86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
172 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
173 bne freq_out @ leave if SDR, no DLL function
175 /* With DDR, we need to take care of the DLL for the frequency change */
180 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
[all …]
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| D | sdrc2xxx.c | 32 /* Memory timing, DLL mode flags */
58 * Check the DLL lock state, and return tue if running in unlock mode.
59 * This is needed to compensate for the shifted DLL value in unlock mode.
133 /* With DDR we need to determine the low frequency DLL value */ in omap2xxx_sdrc_init_params()
150 /* set fast timings with DLL filter disabled */ in omap2xxx_sdrc_init_params()
164 /* 90 degree phase for anything below 133MHz + disable DLL filter */ in omap2xxx_sdrc_init_params()
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| /kernel/linux/linux-4.19/arch/arm/mach-omap2/ |
| D | sleep24xx.S | 45 * R0 : DLL ctrl value pre-Sleep
50 * when we get called, but the DLL probably isn't. We will wait a bit more in
51 * case the DPLL isn't quite there yet. The code will wait on DLL for DDR even
62 * The DLL load value is not kept in RETENTION or OFF. It needs to be restored
74 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
90 strne r0, [r1] @ rewrite DLLA to force DLL reload
92 strne r0, [r1] @ rewrite DLLB to force DLL reload
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| D | sram243x.S | 59 /* dll lock mode */
66 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
69 bl i_dll_wait @ wait for dll to lock
71 /* get dll value */
98 /* ensure the DLL has relocked */
100 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
186 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
187 bne freq_out @ leave if SDR, no DLL function
189 /* With DDR, we need to take care of the DLL for the frequency change */
194 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
[all …]
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| D | sram242x.S | 59 /* dll lock mode */
66 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
69 bl i_dll_wait @ wait for dll to lock
71 /* get dll value */
98 /* ensure the DLL has relocked */
100 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
186 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
187 bne freq_out @ leave if SDR, no DLL function
189 /* With DDR, we need to take care of the DLL for the frequency change */
194 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
[all …]
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| D | sdrc2xxx.c | 35 /* Memory timing, DLL mode flags */
61 * Check the DLL lock state, and return tue if running in unlock mode.
62 * This is needed to compensate for the shifted DLL value in unlock mode.
136 /* With DDR we need to determine the low frequency DLL value */ in omap2xxx_sdrc_init_params()
153 /* set fast timings with DLL filter disabled */ in omap2xxx_sdrc_init_params()
167 /* 90 degree phase for anything below 133MHz + disable DLL filter */ in omap2xxx_sdrc_init_params()
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/mmc/ |
| D | sdhci-cadence.txt | 23 PHY DLL input delays:
52 PHY DLL clock delays:
56 - cdns,phy-dll-delay-sdclk:
60 - cdns,phy-dll-delay-sdclk-hsmmc:
64 - cdns,phy-dll-delay-strobe:
79 cdns,phy-dll-delay-sdclk = <0>;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | cdns,sdhci.yaml | 32 # PHY DLL input delays:
82 # PHY DLL clock delays:
90 cdns,phy-dll-delay-sdclk:
98 cdns,phy-dll-delay-sdclk-hsmmc:
106 cdns,phy-dll-delay-strobe:
133 cdns,phy-dll-delay-sdclk = <0>;
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| D | fsl-imx-esdhc.yaml | 60 This is used to set the clock delay for DLL(Delay Line) on override mode
63 chapter, DLL (Delay Line) section in RM for details.
95 fsl,strobe-dll-delay-target:
98 Specify the strobe dll control slave delay target.
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| /kernel/linux/linux-4.19/arch/x86/boot/ |
| D | early_serial_console.c | 21 #define DLL 0 /* Divisor Latch Low */ macro
39 outb(divisor & 0xff, port + DLL); in early_serial_init()
104 unsigned char lcr, dll, dlh; in probe_baud() local
109 dll = inb(port + DLL); in probe_baud()
112 quot = (dlh << 8) | dll; in probe_baud()
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| /kernel/linux/linux-5.10/arch/x86/boot/ |
| D | early_serial_console.c | 21 #define DLL 0 /* Divisor Latch Low */ macro
39 outb(divisor & 0xff, port + DLL); in early_serial_init()
104 unsigned char lcr, dll, dlh; in probe_baud() local
109 dll = inb(port + DLL); in probe_baud()
112 quot = (dlh << 8) | dll; in probe_baud()
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| /kernel/linux/linux-5.10/arch/powerpc/kernel/ |
| D | udbg_16550.c | 97 unsigned int dll, base_bauds; in udbg_uart_setup() local
108 dll = base_bauds / speed; in udbg_uart_setup()
114 udbg_uart_out(UART_DLL, dll & 0xff); in udbg_uart_setup()
115 udbg_uart_out(UART_DLM, dll >> 8); in udbg_uart_setup()
126 unsigned int dll, dlm, divisor, prescaler, speed; in udbg_probe_uart_speed() local
135 dll = udbg_uart_in(UART_DLL); in udbg_probe_uart_speed()
137 divisor = dlm << 8 | dll; in udbg_probe_uart_speed()
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| /kernel/linux/linux-4.19/arch/powerpc/kernel/ |
| D | udbg_16550.c | 101 unsigned int dll, base_bauds; in udbg_uart_setup() local
112 dll = base_bauds / speed; in udbg_uart_setup()
118 udbg_uart_out(UART_DLL, dll & 0xff); in udbg_uart_setup()
119 udbg_uart_out(UART_DLM, dll >> 8); in udbg_uart_setup()
130 unsigned int dll, dlm, divisor, prescaler, speed; in udbg_probe_uart_speed() local
139 dll = udbg_uart_in(UART_DLL); in udbg_probe_uart_speed()
141 divisor = dlm << 8 | dll; in udbg_probe_uart_speed()
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| /kernel/linux/linux-5.10/drivers/phy/intel/ |
| D | phy-intel-keembay-emmc.c | 76 dev_err(&phy->dev, "turn off the dll failed: %d\n", ret); in keembay_emmc_phy_power()
131 /* Set the frequency of the DLL operation */ in keembay_emmc_phy_power()
135 dev_err(&phy->dev, "set the frequency of dll failed:%d\n", ret); in keembay_emmc_phy_power()
139 /* Turn on the DLL */ in keembay_emmc_phy_power()
143 dev_err(&phy->dev, "turn on the dll failed: %d\n", ret); in keembay_emmc_phy_power()
148 * We turned on the DLL even though the rate was 0 because we the in keembay_emmc_phy_power()
149 * clock might be turned on later. ...but we can't wait for the DLL in keembay_emmc_phy_power()
160 * After enabling analog DLL circuits docs say that we need 10.2 us if in keembay_emmc_phy_power()
168 * NOTE: There appear to be corner cases where the DLL seems to take in keembay_emmc_phy_power()
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| D | phy-intel-lgm-emmc.c | 110 /* Set the frequency of the DLL operation */ in intel_emmc_phy_power()
114 dev_err(&phy->dev, "set the frequency of dll failed:%d\n", ret); in intel_emmc_phy_power()
118 /* Turn on the DLL */ in intel_emmc_phy_power()
122 dev_err(&phy->dev, "turn on the dll failed: %d\n", ret); in intel_emmc_phy_power()
127 * After enabling analog DLL circuits docs say that we need 10.2 us if in intel_emmc_phy_power()
135 * NOTE: There appear to be corner cases where the DLL seems to take in intel_emmc_phy_power()
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/devfreq/ |
| D | rk3399_dmc.txt | 60 - rockchip,dram_dll_dis_freq : Defines the DDR3 DLL bypass frequency in MHz.
62 DDR3 DLL will be bypassed. Note: if DLL was bypassed,
65 - rockchip,phy_dll_dis_freq : Defines the PHY dll bypass frequency in
67 DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.
68 Note: PHY DLL and PHY ODT are independent.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/devfreq/ |
| D | rk3399_dmc.txt | 62 - rockchip,dram_dll_dis_freq : Defines the DDR3 DLL bypass frequency in MHz.
64 DDR3 DLL will be bypassed. Note: if DLL was bypassed,
67 - rockchip,phy_dll_dis_freq : Defines the PHY dll bypass frequency in
69 DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.
70 Note: PHY DLL and PHY ODT are independent.
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| /kernel/linux/linux-4.19/drivers/phy/rockchip/ |
| D | phy-rockchip-emmc.c | 149 * pretty spot on for the DLL range, so warn if we're too in rockchip_emmc_phy_power()
185 /* Set the frequency of the DLL operation */ in rockchip_emmc_phy_power()
191 /* Turn on the DLL */ in rockchip_emmc_phy_power()
199 * We turned on the DLL even though the rate was 0 because we the in rockchip_emmc_phy_power()
200 * clock might be turned on later. ...but we can't wait for the DLL in rockchip_emmc_phy_power()
211 * After enabling analog DLL circuits docs say that we need 10.2 us if in rockchip_emmc_phy_power()
219 * NOTE: There appear to be corner cases where the DLL seems to take in rockchip_emmc_phy_power()
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| /kernel/linux/linux-5.10/drivers/mmc/host/ |
| D | sdhci-pci-o2micro.c | 174 * This function is used to detect dll lock status.
175 * Since the dll lock status bit will toggle randomly
225 * This function is used to fix o2 dll shift issue.
268 * need wait at least 5ms for dll status stable, in sdhci_o2_dll_recovery()
278 pr_warn("%s: DLL unlocked when dll_adjust_count is %d.\n", in sdhci_o2_dll_recovery()
291 pr_err("%s: DLL adjust over max times\n", in sdhci_o2_dll_recovery()
325 /* wait DLL lock, timeout value 5ms */ in sdhci_o2_execute_tuning()
328 pr_warn("%s: DLL can't lock in 5ms after force L0 during tuning.\n", in sdhci_o2_execute_tuning()
331 * Judge the tuning reason, whether caused by dll shift in sdhci_o2_execute_tuning()
332 * If cause by dll shift, should call sdhci_o2_dll_recovery in sdhci_o2_execute_tuning()
[all …]
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| D | sdhci-esdhc.h | 89 /* DLL Config 0 Register */
95 /* DLL Config 1 Register */
99 /* DLL Status 0 Register */
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| /kernel/linux/linux-5.10/drivers/phy/rockchip/ |
| D | phy-rockchip-emmc.c | 142 * pretty spot on for the DLL range, so warn if we're too in rockchip_emmc_phy_power()
178 /* Set the frequency of the DLL operation */ in rockchip_emmc_phy_power()
184 /* Turn on the DLL */ in rockchip_emmc_phy_power()
192 * We turned on the DLL even though the rate was 0 because we the in rockchip_emmc_phy_power()
193 * clock might be turned on later. ...but we can't wait for the DLL in rockchip_emmc_phy_power()
204 * After enabling analog DLL circuits docs say that we need 10.2 us if in rockchip_emmc_phy_power()
212 * NOTE: There appear to be corner cases where the DLL seems to take in rockchip_emmc_phy_power()
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| /kernel/linux/linux-4.19/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | gddr3.c | 73 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi; in nvkm_gddr3_calc() local
80 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_gddr3_calc()
89 DLL = !(ram->mr[1] & 0x1); in nvkm_gddr3_calc()
117 ram->mr[1] |= !DLL << 6; in nvkm_gddr3_calc()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | gddr3.c | 73 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi; in nvkm_gddr3_calc() local
80 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_gddr3_calc()
89 DLL = !(ram->mr[1] & 0x1); in nvkm_gddr3_calc()
117 ram->mr[1] |= !DLL << 6; in nvkm_gddr3_calc()
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