| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/ |
| D | lpc1850-dmamux.txt | 1 NXP LPC18xx/43xx DMA MUX (DMA request router)
4 - compatible: "nxp,lpc1850-dmamux"
5 - reg: Memory map for accessing module
6 - #dma-cells: Should be set to <3>.
7 * 1st cell contain the master dma request signal
8 * 2nd cell contain the mux value (0-3) for the peripheral
11 - dma-requests: Number of DMA requests for the mux
12 - dma-masters: phandle pointing to the DMA controller
14 The DMA controller node need to have the following poroperties:
15 - dma-requests: Number of DMA requests the controller can handle
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| D | ti-dma-crossbar.txt | 1 Texas Instruments DMA Crossbar (DMA request router)
4 - compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar
5 "ti,am335x-edma-crossbar" for AM335x and AM437x
6 - reg: Memory map for accessing module
7 - #dma-cells: Should be set to to match with the DMA controller's dma-cells
8 for ti,dra7-dma-crossbar and <3> for ti,am335x-edma-crossbar.
9 - dma-requests: Number of DMA requests the crossbar can receive
10 - dma-masters: phandle pointing to the DMA controller
12 The DMA controller node need to have the following poroperties:
13 - dma-requests: Number of DMA requests the controller can handle
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| D | fsl-imx-dma.txt | 1 * Freescale Direct Memory Access (DMA) Controller for i.MX
3 This document will only describe differences to the generic DMA Controller and
4 DMA request bindings as described in dma/dma.txt .
6 * DMA controller
9 - compatible : Should be "fsl,<chip>-dma". chip can be imx1, imx21 or imx27
10 - reg : Should contain DMA registers location and length
11 - interrupts : First item should be DMA interrupt, second one is optional and
12 should contain DMA Error interrupt
13 - #dma-cells : Has to be 1. imx-dma does not support anything else.
16 - #dma-channels : Number of DMA channels supported. Should be 16.
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| D | mtk-uart-apdma.txt | 4 - compatible should contain:
5 * "mediatek,mt2712-uart-dma" for MT2712 compatible APDMA
6 * "mediatek,mt6577-uart-dma" for MT6577 and all of the above
8 - reg: The base address of the APDMA register bank.
10 - interrupts: A single interrupt specifier.
11 One interrupt per dma-requests, or 8 if no dma-requests property is present
13 - dma-requests: The number of DMA channels
15 - clocks : Must contain an entry for each entry in clock-names.
16 See ../clocks/clock-bindings.txt for details.
17 - clock-names: The APDMA clock for register accesses
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| D | dma-router.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/dma-router.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DMA Router Generic Binding
10 - Vinod Koul <vkoul@kernel.org>
13 - $ref: "dma-common.yaml#"
16 DMA routers are transparent IP blocks used to route DMA request
17 lines from devices to the DMA controller. Some SoCs (like TI DRA7x)
18 have more peripherals integrated with DMA requests than what the DMA
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| D | owl-dma.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/owl-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Actions Semi Owl SoCs DMA controller
10 The OWL DMA is a general-purpose direct memory access controller capable of
11 supporting 10 and 12 independent DMA channels for S700 and S900 SoCs
15 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
18 - $ref: "dma-controller.yaml#"
23 - actions,s900-dma
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| D | arm-pl330.txt | 1 * ARM PrimeCell PL330 DMA Controller
3 The ARM PrimeCell PL330 DMA controller can move blocks of memory contents
7 - compatible: should include both "arm,pl330" and "arm,primecell".
8 - reg: physical base address of the controller and length of memory mapped
10 - interrupts: interrupt number to the cpu.
13 - dma-coherent : Present if dma operations are coherent
14 - #dma-cells: must be <1>. used to represent the number of integer
16 - dma-channels: contains the total number of DMA channels supported by the DMAC
17 - dma-requests: contains the total number of DMA requests supported by the DMAC
18 - arm,pl330-broken-no-flushp: quirk for avoiding to execute DMAFLUSHP
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| D | zxdma.txt | 1 * ZTE ZX296702 DMA controller
4 - compatible: Should be "zte,zx296702-dma"
5 - reg: Should contain DMA registers location and length.
6 - interrupts: Should contain one interrupt shared by all channel
7 - #dma-cells: see dma.txt, should be 1, para number
8 - dma-channels: physical channels supported
9 - dma-requests: virtual channels supported, each virtual channel
11 - clocks: clock required
16 dma: dma-controller@09c00000{
17 compatible = "zte,zx296702-dma";
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/dma/ |
| D | lpc1850-dmamux.txt | 1 NXP LPC18xx/43xx DMA MUX (DMA request router)
4 - compatible: "nxp,lpc1850-dmamux"
5 - reg: Memory map for accessing module
6 - #dma-cells: Should be set to <3>.
7 * 1st cell contain the master dma request signal
8 * 2nd cell contain the mux value (0-3) for the peripheral
11 - dma-requests: Number of DMA requests for the mux
12 - dma-masters: phandle pointing to the DMA controller
14 The DMA controller node need to have the following poroperties:
15 - dma-requests: Number of DMA requests the controller can handle
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| D | stm32-dmamux.txt | 1 STM32 DMA MUX (DMA request router)
4 - compatible: "st,stm32h7-dmamux"
5 - reg: Memory map for accessing module
6 - #dma-cells: Should be set to <3>.
8 Second is DMA channel configuration
11 stm32-dma.txt documentation binding file
12 - dma-masters: Phandle pointing to the DMA controllers.
13 Several controllers are allowed. Only "st,stm32-dma" DMA
17 - dma-channels : Number of DMA requests supported.
18 - dma-requests : Number of DMAMUX requests supported.
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| D | ti-dma-crossbar.txt | 1 Texas Instruments DMA Crossbar (DMA request router)
4 - compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar
5 "ti,am335x-edma-crossbar" for AM335x and AM437x
6 - reg: Memory map for accessing module
7 - #dma-cells: Should be set to to match with the DMA controller's dma-cells
8 for ti,dra7-dma-crossbar and <3> for ti,am335x-edma-crossbar.
9 - dma-requests: Number of DMA requests the crossbar can receive
10 - dma-masters: phandle pointing to the DMA controller
12 The DMA controller node need to have the following poroperties:
13 - dma-requests: Number of DMA requests the controller can handle
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| D | dma.txt | 1 * Generic DMA Controller and DMA request bindings
3 Generic binding to provide a way for a driver using DMA Engine to retrieve the
4 DMA request or channel information that goes from a hardware device to a DMA
8 * DMA controller
11 - #dma-cells: Must be at least 1. Used to provide DMA controller
12 specific information. See DMA client binding below for
16 - dma-channels: Number of DMA channels supported by the controller.
17 - dma-requests: Number of DMA request signals supported by the
22 dma: dma@48000000 {
23 compatible = "ti,omap-sdma";
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| D | fsl-imx-dma.txt | 1 * Freescale Direct Memory Access (DMA) Controller for i.MX
3 This document will only describe differences to the generic DMA Controller and
4 DMA request bindings as described in dma/dma.txt .
6 * DMA controller
9 - compatible : Should be "fsl,<chip>-dma". chip can be imx1, imx21 or imx27
10 - reg : Should contain DMA registers location and length
11 - interrupts : First item should be DMA interrupt, second one is optional and
12 should contain DMA Error interrupt
13 - #dma-cells : Has to be 1. imx-dma does not support anything else.
16 - #dma-channels : Number of DMA channels supported. Should be 16.
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| D | stm32-dma.txt | 1 * STMicroelectronics STM32 DMA controller
3 The STM32 DMA is a general-purpose direct memory access controller capable of
4 supporting 8 independent DMA channels. Each channel can have up to 8 requests.
7 - compatible: Should be "st,stm32-dma"
8 - reg: Should contain DMA registers location and length. This should include
9 all of the per-channel registers.
10 - interrupts: Should contain all of the per-channel DMA interrupts in
11 ascending order with respect to the DMA channel index.
12 - clocks: Should contain the input clock of the DMA instance.
13 - #dma-cells : Must be <4>. See DMA client paragraph for more details.
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| D | arm-pl330.txt | 1 * ARM PrimeCell PL330 DMA Controller
3 The ARM PrimeCell PL330 DMA controller can move blocks of memory contents
7 - compatible: should include both "arm,pl330" and "arm,primecell".
8 - reg: physical base address of the controller and length of memory mapped
10 - interrupts: interrupt number to the cpu.
13 - dma-coherent : Present if dma operations are coherent
14 - #dma-cells: must be <1>. used to represent the number of integer
16 - dma-channels: contains the total number of DMA channels supported by the DMAC
17 - dma-requests: contains the total number of DMA requests supported by the DMAC
18 - arm,pl330-broken-no-flushp: quirk for avoiding to execute DMAFLUSHP
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| D | stm32-mdma.txt | 3 The STM32 MDMA is a general-purpose direct memory access controller capable of
4 supporting 64 independent DMA channels with 256 HW requests.
7 - compatible: Should be "st,stm32h7-mdma"
8 - reg: Should contain MDMA registers location and length. This should include
9 all of the per-channel registers.
10 - interrupts: Should contain the MDMA interrupt.
11 - clocks: Should contain the input clock of the DMA instance.
12 - resets: Reference to a reset controller asserting the DMA controller.
13 - #dma-cells : Must be <5>. See DMA client paragraph for more details.
16 - dma-channels: Number of DMA channels supported by the controller.
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| D | zxdma.txt | 1 * ZTE ZX296702 DMA controller
4 - compatible: Should be "zte,zx296702-dma"
5 - reg: Should contain DMA registers location and length.
6 - interrupts: Should contain one interrupt shared by all channel
7 - #dma-cells: see dma.txt, should be 1, para number
8 - dma-channels: physical channels supported
9 - dma-requests: virtual channels supported, each virtual channel
11 - clocks: clock required
16 dma: dma-controller@09c00000{
17 compatible = "zte,zx296702-dma";
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| D | owl-dma.txt | 1 * Actions Semi Owl SoCs DMA controller
3 This binding follows the generic DMA bindings defined in dma.txt.
6 - compatible: Should be "actions,s900-dma".
7 - reg: Should contain DMA registers location and length.
8 - interrupts: Should contain 4 interrupts shared by all channel.
9 - #dma-cells: Must be <1>. Used to represent the number of integer
11 - dma-channels: Physical channels supported.
12 - dma-requests: Number of DMA request signals supported by the controller.
13 Refer to Documentation/devicetree/bindings/dma/dma.txt
14 - clocks: Phandle and Specifier of the clock feeding the DMA controller.
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| /kernel/linux/linux-5.10/Documentation/vm/ |
| D | balance.rst | 15 overhead of page reclaim. This may happen for opportunistic high-order
16 allocation requests that have order-0 fallback options. In such cases,
19 __GFP_IO allocation requests are made to prevent file system deadlocks.
21 In the absence of non sleepable allocation requests, it seems detrimental
26 That being said, the kernel should try to fulfill requests for direct
28 the dma pool, so as to keep the dma pool filled for dma requests (atomic
30 OTOH, if there is a lot of free dma pages, it is preferable to satisfy
31 regular memory requests by allocating one from the dma pool, instead
36 right ratio of dma and regular memory, it is quite possible that balancing
37 would not be done even when the dma zone was completely empty. 2.2 has
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| /kernel/linux/linux-4.19/Documentation/vm/ |
| D | balance.rst | 15 overhead of page reclaim. This may happen for opportunistic high-order
16 allocation requests that have order-0 fallback options. In such cases,
19 __GFP_IO allocation requests are made to prevent file system deadlocks.
21 In the absence of non sleepable allocation requests, it seems detrimental
26 That being said, the kernel should try to fulfill requests for direct
28 the dma pool, so as to keep the dma pool filled for dma requests (atomic
30 OTOH, if there is a lot of free dma pages, it is preferable to satisfy
31 regular memory requests by allocating one from the dma pool, instead
36 right ratio of dma and regular memory, it is quite possible that balancing
37 would not be done even when the dma zone was completely empty. 2.2 has
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| /kernel/linux/linux-4.19/drivers/dma/ |
| D | stm32-dmamux.c | 5 * Pierre-Yves Mordret <pierre-yves.mordret@st.com>
18 * DMA Router driver for STM32 DMA MUX
20 * Based on TI DMA Crossbar driver
50 u32 dma_requests; /* Number of DMA requests connected to DMAMUX */
51 u32 dmamux_requests; /* Number of DMA requests routed toward DMAs */
53 unsigned long *dma_inuse; /* Used DMA channel */
54 u32 dma_reqs[]; /* Number of DMA Request per DMA masters.
55 * [0] holds number of DMA Masters.
76 /* Clear dma request */ in stm32_dmamux_free()
77 spin_lock_irqsave(&dmamux->lock, flags); in stm32_dmamux_free()
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| /kernel/linux/linux-5.10/drivers/dma/ |
| D | stm32-dmamux.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Pierre-Yves Mordret <pierre-yves.mordret@st.com>
8 * DMA Router driver for STM32 DMA MUX
10 * Based on TI DMA Crossbar driver
39 u32 dma_requests; /* Number of DMA requests connected to DMAMUX */
40 u32 dmamux_requests; /* Number of DMA requests routed toward DMAs */
42 unsigned long *dma_inuse; /* Used DMA channel */
46 u32 dma_reqs[]; /* Number of DMA Request per DMA masters.
47 * [0] holds number of DMA Masters.
68 /* Clear dma request */ in stm32_dmamux_free()
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| /kernel/linux/linux-5.10/drivers/dma/ti/ |
| D | dma-crossbar.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
24 .compatible = "ti,dra7-dma-crossbar",
28 .compatible = "ti,am335x-edma-crossbar",
43 u32 dma_requests; /* number of DMA requests on eDMA */
59 writeb_relaxed(val, iomem + (63 - event % 4)); in ti_am335x_xbar_write()
70 map->mux_val, map->dma_line); in ti_am335x_xbar_free()
72 ti_am335x_xbar_write(xbar->iomem, map->dma_line, 0); in ti_am335x_xbar_free()
79 struct platform_device *pdev = of_find_device_by_node(ofdma->of_node); in ti_am335x_xbar_route_allocate()
83 if (dma_spec->args_count != 3) in ti_am335x_xbar_route_allocate()
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| /kernel/linux/linux-4.19/drivers/dma/ti/ |
| D | dma-crossbar.c | 2 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
28 .compatible = "ti,dra7-dma-crossbar",
32 .compatible = "ti,am335x-edma-crossbar",
47 u32 dma_requests; /* number of DMA requests on eDMA */
63 writeb_relaxed(val, iomem + (63 - event % 4)); in ti_am335x_xbar_write()
74 map->mux_val, map->dma_line); in ti_am335x_xbar_free()
76 ti_am335x_xbar_write(xbar->iomem, map->dma_line, 0); in ti_am335x_xbar_free()
83 struct platform_device *pdev = of_find_device_by_node(ofdma->of_node); in ti_am335x_xbar_route_allocate()
87 if (dma_spec->args_count != 3) in ti_am335x_xbar_route_allocate()
88 return ERR_PTR(-EINVAL); in ti_am335x_xbar_route_allocate()
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| /kernel/linux/linux-4.19/Documentation/rapidio/ |
| D | mport_cdev.txt | 5 ----------------
6 1.0.0 - Initial driver release.
21 for user-space applications. Most of RapidIO operations are supported through
28 Using available set of ioctl commands user-space applications can perform
31 - Reads and writes from/to configuration registers of mport devices
33 - Reads and writes from/to configuration registers of remote RapidIO devices.
36 - Set RapidIO Destination ID for mport devices (RIO_MPORT_MAINT_HDID_SET)
37 - Set RapidIO Component Tag for mport devices (RIO_MPORT_MAINT_COMPTAG_SET)
38 - Query logical index of mport devices (RIO_MPORT_MAINT_PORT_IDX_GET)
39 - Query capabilities and RapidIO link configuration of mport devices
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