| /kernel/linux/linux-5.10/drivers/phy/rockchip/ |
| D | phy-rockchip-dp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip DP PHY driver
6 * Author: Yakir Yang <ykk@@rock-chips.com>
13 #include <linux/phy/phy.h>
32 static int rockchip_set_phy_state(struct phy *phy, bool enable) in rockchip_set_phy_state() argument
34 struct rockchip_dp_phy *dp = phy_get_drvdata(phy); in rockchip_set_phy_state() local
38 ret = regmap_write(dp->grf, GRF_SOC_CON12, in rockchip_set_phy_state()
42 dev_err(dp->dev, "Can't enable PHY power %d\n", ret); in rockchip_set_phy_state()
46 ret = clk_prepare_enable(dp->phy_24m); in rockchip_set_phy_state()
48 clk_disable_unprepare(dp->phy_24m); in rockchip_set_phy_state()
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| /kernel/linux/linux-4.19/drivers/phy/rockchip/ |
| D | phy-rockchip-dp.c | 2 * Rockchip DP PHY driver
5 * Author: Yakir Yang <ykk@@rock-chips.com>
16 #include <linux/phy/phy.h>
35 static int rockchip_set_phy_state(struct phy *phy, bool enable) in rockchip_set_phy_state() argument
37 struct rockchip_dp_phy *dp = phy_get_drvdata(phy); in rockchip_set_phy_state() local
41 ret = regmap_write(dp->grf, GRF_SOC_CON12, in rockchip_set_phy_state()
45 dev_err(dp->dev, "Can't enable PHY power %d\n", ret); in rockchip_set_phy_state()
49 ret = clk_prepare_enable(dp->phy_24m); in rockchip_set_phy_state()
51 clk_disable_unprepare(dp->phy_24m); in rockchip_set_phy_state()
53 ret = regmap_write(dp->grf, GRF_SOC_CON12, in rockchip_set_phy_state()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/exynos/ |
| D | exynos_dp.txt | 5 -dp-controller node
6 -dptx-phy node(defined inside dp-controller node)
8 For the DP-PHY initialization, we use the dptx-phy node.
9 Required properties for dptx-phy: deprecated, use phys and phy-names
10 -reg: deprecated
11 Base address of DP PHY register.
12 -samsung,enable-mask: deprecated
13 The bit-mask used to enable/disable DP PHY.
15 For the Panel initialization, we read data from dp-controller node.
16 Required properties for dp-controller:
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/display/exynos/ |
| D | exynos_dp.txt | 5 -dp-controller node
6 -dptx-phy node(defined inside dp-controller node)
8 For the DP-PHY initialization, we use the dptx-phy node.
9 Required properties for dptx-phy: deprecated, use phys and phy-names
10 -reg: deprecated
11 Base address of DP PHY register.
12 -samsung,enable-mask: deprecated
13 The bit-mask used to enable/disable DP PHY.
15 For the Panel initialization, we read data from dp-controller node.
16 Required properties for dp-controller:
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| /kernel/linux/linux-5.10/drivers/gpu/drm/xlnx/ |
| D | zynqmp_dp.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
31 #include <linux/phy/phy.h>
40 MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value in msec (default: 50)");
47 MODULE_PARM_DESC(power_on_delay_ms, "DP power on delay in msec (default: 4)");
182 /* PHY configuration and status registers */
242 * struct zynqmp_dp_link_config - Common link config between source and sink
252 * struct zynqmp_dp_mode - Configured mode of DisplayPort
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | qcom,qmp-usb3-dp-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-usb3-dp-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm QMP USB3 DP PHY controller
11 - Manu Gautam <mgautam@codeaurora.org>
16 - qcom,sc7180-qmp-usb3-dp-phy
17 - qcom,sc7180-qmp-usb3-phy
18 - qcom,sdm845-qmp-usb3-dp-phy
19 - qcom,sdm845-qmp-usb3-phy
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| D | phy-rockchip-typec.txt | 1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
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| D | rockchip-dp-phy.txt | 1 Rockchip specific extensions to the Analogix Display Port PHY
2 ------------------------------------
5 - compatible : should be one of the following supported values:
6 - "rockchip.rk3288-dp-phy"
7 - clocks: from common clock binding: handle to dp clock.
9 - clock-names: from common clock binding:
11 - #phy-cells : from the generic PHY bindings, must be 0;
16 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
20 edp_phy: edp-phy {
21 compatible = "rockchip,rk3288-dp-phy";
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| /kernel/linux/linux-5.10/drivers/net/ethernet/broadcom/bnx2x/ |
| D | bnx2x_link.c | 1 /* Copyright 2008-2013 Broadcom Corporation
8 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
32 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy,
43 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
205 (_phy)->def_md_devad, \
211 (_phy)->def_md_devad, \
217 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
239 * bnx2x_check_lfa - This function checks if link reinitialization is required,
251 struct bnx2x *bp = params->bp; in bnx2x_check_lfa()
254 REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
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| /kernel/linux/linux-4.19/drivers/net/ethernet/broadcom/bnx2x/ |
| D | bnx2x_link.c | 1 /* Copyright 2008-2013 Broadcom Corporation
8 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
32 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy,
43 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
205 (_phy)->def_md_devad, \
211 (_phy)->def_md_devad, \
217 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
239 * bnx2x_check_lfa - This function checks if link reinitialization is required,
251 struct bnx2x *bp = params->bp; in bnx2x_check_lfa()
254 REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/bridge/ |
| D | analogix_dp.txt | 3 Required properties for dp-controller:
4 -compatible:
6 * "samsung,exynos5-dp"
7 * "rockchip,rk3288-dp"
8 * "rockchip,rk3399-edp"
9 -reg:
12 -interrupts:
14 -clocks:
15 from common clock binding: handle to dp clock.
16 -clock-names:
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| D | cdns,mhdp8546.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Swapnil Jakhade <sjakhade@cadence.com>
11 - Yuti Amonkar <yamonkar@cadence.com>
16 - cdns,mhdp8546
17 - ti,j721e-mhdp8546
23 - description:
24 Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
26 included in the associated PHY.
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/display/bridge/ |
| D | analogix_dp.txt | 3 Required properties for dp-controller:
4 -compatible:
6 * "samsung,exynos5-dp"
7 * "rockchip,rk3288-dp"
8 * "rockchip,rk3399-edp"
9 -reg:
12 -interrupts:
14 -clocks:
15 from common clock binding: handle to dp clock.
16 -clock-names:
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| /kernel/linux/linux-4.19/net/dsa/ |
| D | port.c | 4 * Copyright (c) 2017 Savoir-faire Linux Inc.
20 static int dsa_port_notify(const struct dsa_port *dp, unsigned long e, void *v) in dsa_port_notify() argument
22 struct raw_notifier_head *nh = &dp->ds->dst->nh; in dsa_port_notify()
30 int dsa_port_set_state(struct dsa_port *dp, u8 state, in dsa_port_set_state() argument
33 struct dsa_switch *ds = dp->ds; in dsa_port_set_state()
34 int port = dp->index; in dsa_port_set_state()
37 return ds->ops->port_stp_state_set ? 0 : -EOPNOTSUPP; in dsa_port_set_state()
39 if (ds->ops->port_stp_state_set) in dsa_port_set_state()
40 ds->ops->port_stp_state_set(ds, port, state); in dsa_port_set_state()
42 if (ds->ops->port_fast_age) { in dsa_port_set_state()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/rockchip/ |
| D | cdn-dp-core.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Chris Zhong <zyw@rock-chips.com>
12 #include <linux/phy/phy.h>
16 #include <sound/hdmi-codec.h>
25 #include "cdn-dp-core.h"
26 #include "cdn-dp-reg.h"
55 { .compatible = "rockchip,rk3399-cdn-dp",
62 static int cdn_dp_grf_write(struct cdn_dp_device *dp, in cdn_dp_grf_write() argument
67 ret = clk_prepare_enable(dp->grf_clk); in cdn_dp_grf_write()
69 DRM_DEV_ERROR(dp->dev, "Failed to prepare_enable grf clock\n"); in cdn_dp_grf_write()
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| /kernel/linux/linux-4.19/drivers/gpu/drm/rockchip/ |
| D | cdn-dp-core.c | 3 * Author: Chris Zhong <zyw@rock-chips.com>
29 #include <linux/phy/phy.h>
31 #include <sound/hdmi-codec.h>
33 #include "cdn-dp-core.h"
34 #include "cdn-dp-reg.h"
63 { .compatible = "rockchip,rk3399-cdn-dp",
70 static int cdn_dp_grf_write(struct cdn_dp_device *dp, in cdn_dp_grf_write() argument
75 ret = clk_prepare_enable(dp->grf_clk); in cdn_dp_grf_write()
77 DRM_DEV_ERROR(dp->dev, "Failed to prepare_enable grf clock\n"); in cdn_dp_grf_write()
81 ret = regmap_write(dp->grf, reg, val); in cdn_dp_grf_write()
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| /kernel/linux/linux-5.10/drivers/phy/samsung/ |
| D | phy-exynos-dp-video.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung Exynos SoC series Display Port PHY driver
17 #include <linux/phy/phy.h>
20 #include <linux/soc/samsung/exynos-regs-pmu.h>
31 static int exynos_dp_video_phy_power_on(struct phy *phy) in exynos_dp_video_phy_power_on() argument
33 struct exynos_dp_video_phy *state = phy_get_drvdata(phy); in exynos_dp_video_phy_power_on()
35 /* Disable power isolation on DP-PHY */ in exynos_dp_video_phy_power_on()
36 return regmap_update_bits(state->regs, state->drvdata->phy_ctrl_offset, in exynos_dp_video_phy_power_on()
40 static int exynos_dp_video_phy_power_off(struct phy *phy) in exynos_dp_video_phy_power_off() argument
42 struct exynos_dp_video_phy *state = phy_get_drvdata(phy); in exynos_dp_video_phy_power_off()
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| /kernel/linux/linux-4.19/drivers/phy/samsung/ |
| D | phy-exynos-dp-video.c | 2 * Samsung EXYNOS SoC series Display Port PHY driver
20 #include <linux/phy/phy.h>
23 #include <linux/soc/samsung/exynos-regs-pmu.h>
34 static int exynos_dp_video_phy_power_on(struct phy *phy) in exynos_dp_video_phy_power_on() argument
36 struct exynos_dp_video_phy *state = phy_get_drvdata(phy); in exynos_dp_video_phy_power_on()
38 /* Disable power isolation on DP-PHY */ in exynos_dp_video_phy_power_on()
39 return regmap_update_bits(state->regs, state->drvdata->phy_ctrl_offset, in exynos_dp_video_phy_power_on()
43 static int exynos_dp_video_phy_power_off(struct phy *phy) in exynos_dp_video_phy_power_off() argument
45 struct exynos_dp_video_phy *state = phy_get_drvdata(phy); in exynos_dp_video_phy_power_off()
47 /* Enable power isolation on DP-PHY */ in exynos_dp_video_phy_power_off()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/ |
| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
2 ccflags-y := -I $(srctree)/$(src)
3 ccflags-y += -I $(srctree)/$(src)/disp/dpu1
4 ccflags-$(CONFIG_DRM_MSM_DSI) += -I $(srctree)/$(src)/dsi
5 ccflags-$(CONFIG_DRM_MSM_DP) += -I $(srctree)/$(src)/dp
7 msm-y := \
99 msm-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o \
100 dp/dp_debug.o
102 msm-$(CONFIG_DRM_MSM_GPU_STATE) += adreno/a6xx_gpu_state.o
104 msm-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/phy/ |
| D | phy-rockchip-typec.txt | 1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
[all …]
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| /kernel/linux/linux-4.19/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_debugfs.c | 34 * get/ set DP configuration: lane_count, link_rate, spread_spectrum
44 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings
46 * --- to get dp configuration
50 * It will list current, verified, reported, preferred dp configuration.
51 * current -- for current video mode
52 * verified --- maximum configuration which pass link training
53 * reported --- DP rx report caps (DPCD register offset 0, 1 2)
54 * preferred --- user force settings
56 * --- set (or force) dp configuration
77 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; in dp_link_settings_read()
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| /kernel/linux/linux-5.10/net/dsa/ |
| D | port.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2017 Savoir-faire Linux Inc.
22 struct raw_notifier_head *nh = &dst->nh; in dsa_broadcast()
33 static int dsa_port_notify(const struct dsa_port *dp, unsigned long e, void *v) in dsa_port_notify() argument
35 struct raw_notifier_head *nh = &dp->ds->dst->nh; in dsa_port_notify()
43 int dsa_port_set_state(struct dsa_port *dp, u8 state, in dsa_port_set_state() argument
46 struct dsa_switch *ds = dp->ds; in dsa_port_set_state()
47 int port = dp->index; in dsa_port_set_state()
50 return ds->ops->port_stp_state_set ? 0 : -EOPNOTSUPP; in dsa_port_set_state()
52 if (ds->ops->port_stp_state_set) in dsa_port_set_state()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/dp/ |
| D | dp_parser.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
10 #include <linux/phy/phy.h>
11 #include <linux/phy/phy-dp.h>
16 #define DP_LABEL "MDSS DP DISPLAY"
45 * struct dp_display_data - display related device tree data.
48 * @phy_node: reference to phy device
62 * struct dp_ctrl_resource - controller's IO related data
65 * @phy_io: phy's mapped memory address
69 struct phy *phy; member
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_link_encoder.h | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
54 SRI(DP_CONFIG, DP, id), \
55 SRI(DP_DPHY_CNTL, DP, id), \
56 SRI(DP_DPHY_PRBS_CNTL, DP, id), \
57 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
58 SRI(DP_DPHY_SYM0, DP, id), \
59 SRI(DP_DPHY_SYM1, DP, id), \
60 SRI(DP_DPHY_SYM2, DP, id), \
61 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
62 SRI(DP_LINK_CNTL, DP, id), \
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| /kernel/linux/linux-4.19/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_link_encoder.h | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
53 SRI(DP_CONFIG, DP, id), \
54 SRI(DP_DPHY_CNTL, DP, id), \
55 SRI(DP_DPHY_PRBS_CNTL, DP, id), \
56 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
57 SRI(DP_DPHY_SYM0, DP, id), \
58 SRI(DP_DPHY_SYM1, DP, id), \
59 SRI(DP_DPHY_SYM2, DP, id), \
60 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
61 SRI(DP_LINK_CNTL, DP, id), \
[all …]
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