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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/xlnx/
Dxlnx,zynqmp-dpsub.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 +------------------------------------------------------------+
15 +--------+ | +----------------+ +-----------+ |
16 | DPDMA | --->| | --> | Video | Video +-------------+ |
17 | 4x vid | | | | | Rendering | -+--> | | | +------+
18 | 2x aud | | | Audio/Video | --> | Pipeline | | | DisplayPort |---> | PHY0 |
19 +--------+ | | Buffer Manager | +-----------+ | | Source | | +------+
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dqcom,dispcc-sm8x50.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jonathan Marek <jonathan@marek.ca>
17 dt-bindings/clock/qcom,dispcc-sm8150.h
18 dt-bindings/clock/qcom,dispcc-sm8250.h
23 - qcom,sm8150-dispcc
24 - qcom,sm8250-dispcc
28 - description: Board XO source
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Dqcom,sdm845-dispcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sdm845-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Taniya Das <tdas@codeaurora.org>
16 See also dt-bindings/clock/qcom,dispcc-sdm845.h.
20 const: qcom,sdm845-dispcc
27 - description: Board XO source
28 - description: GPLL0 source from GCC
29 - description: GPLL0 div source from GCC
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dfsl-ls1028a-kontron-sl28.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board.
9 /dts-v1/;
10 #include "fsl-ls1028a.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
16 model = "Kontron SMARC-sAL28";
29 compatible = "gpio-keys";
31 power-button {
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/kernel/linux/linux-4.19/arch/arm64/boot/dts/xilinx/
Dzynqmp-zcu102-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
19 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
34 stdout-path = "serial0:115200n8";
42 gpio-keys {
43 compatible = "gpio-keys";
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/xilinx/
Dzynqmp-zcu102-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2015 - 2019, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
19 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
34 stdout-path = "serial0:115200n8";
42 gpio-keys {
43 compatible = "gpio-keys";
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/kernel/linux/linux-4.19/drivers/gpu/drm/i915/
Dintel_dpio_phy.c2 * Copyright © 2014-2016 Intel Corporation
29 * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
35 * IOSF-SB port.
39 * logic. CH0 common lane also contains the IOSF-SB logic for the
49 * each spline is made up of one Physical Access Coding Sub-Layer
51 * and four TX lanes. The TX lanes are used as DP lanes or TMDS
55 * for each channel. This is used for DP AUX communication, but
93 * ---------------------------------
96 * |---------------|---------------| Display PHY
98 * |-------|-------|-------|-------|
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Di915_reg.h18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
41 * registers that are defined solely for the use by function-like macros.
49 * should be defined using function-like macros.
55 * with underscore, followed by a function-like macro choosing the right
64 * OR'd. For convenience, function-like macros may be used to define bit fields,
86 * Try to re-use existing register macro definitions. Only add new macros for
144 * numbers, pick the 0-based __index'th value.
148 #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
151 * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
334 #define RING_PP_DIR_BASE(engine) _MMIO((engine)->mmio_base + 0x228)
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
Dintel_dpio_phy.c2 * Copyright © 2014-2016 Intel Corporation
33 * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
39 * IOSF-SB port.
43 * logic. CH0 common lane also contains the IOSF-SB logic for the
53 * each spline is made up of one Physical Access Coding Sub-Layer
55 * and four TX lanes. The TX lanes are used as DP lanes or TMDS
59 * for each channel. This is used for DP AUX communication, but
97 * ---------------------------------
100 * |---------------|---------------| Display PHY
102 * |-------|-------|-------|-------|
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/kernel/linux/linux-4.19/drivers/gpu/drm/bridge/
Dtc358767.c52 #define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */
84 #define VID_MN_GEN BIT(6) /* Auto-generate M/N values */
151 #define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */
156 #define PHY_M0_RST BIT(8) /* Reset PHY0 Main Channel */
239 ret = regmap_write(tc->regmap, reg, var); \
245 ret = regmap_read(tc->regmap, reg, var); \
272 return ret ?: (((val & cond_mask) == cond_value) ? 0 : -ETIMEDOUT); in tc_poll_timeout()
277 return tc_poll_timeout(tc->regmap, DP0_AUXSTATUS, AUX_BUSY, 0, in tc_aux_wait_busy()
286 ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &value); in tc_aux_get_status()
291 dev_err(tc->dev, "i2c access timeout!\n"); in tc_aux_get_status()
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/kernel/linux/linux-5.10/drivers/gpu/drm/bridge/
Dtc358767.c1 // SPDX-License-Identifier: GPL-2.0-or-later
46 #define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */
108 #define VID_MN_GEN BIT(6) /* Auto-generate M/N values */
191 #define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */
196 #define PHY_M0_RST BIT(8) /* Reset PHY0 Main Channel */
266 /* HPD pin number (0 or 1) or -ENODEV */
292 return regmap_read_poll_timeout(tc->regmap, addr, val, in tc_poll_timeout()
310 ret = regmap_raw_write(tc->regmap, DP0_AUXWDATA(0), auxwdata, count); in tc_aux_write_data()
322 ret = regmap_raw_read(tc->regmap, DP0_AUXRDATA(0), auxrdata, count); in tc_aux_read_data()
333 u32 auxcfg0 = msg->request; in tc_auxcfg0()
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/kernel/linux/linux-5.10/drivers/gpu/drm/xlnx/
Dzynqmp_disp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
27 #include <linux/dma-mapping.h>
43 * --------
45 * The display controller part of ZynqMP DP subsystem, made of the Audio/Video
48 * +------------------------------------------------------------+
49 * +--------+ | +----------------+ +-----------+ |
50 * | DPDMA | --->| | --> | Video | Video +-------------+ |
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
Di915_reg.h18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
44 * registers that are defined solely for the use by function-like macros.
52 * should be defined using function-like macros.
58 * with underscore, followed by a function-like macro choosing the right
68 * function-like macros may be used to define bit fields, but do note that the
87 * Try to re-use existing register macro definitions. Only add new macros for
120 * REG_BIT() - Prepare a u32 bit value
121 * @__n: 0-based bit number
133 * REG_GENMASK() - Prepare a continuous u32 bitmask
134 * @__high: 0-based high bit
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/kernel/linux/patches/linux-4.19/hi3516dv300_patch/
Dhi3516dv300.patch1 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
3 --- a/arch/arm/Kconfig
5 @@ -330,7 +330,7 @@ config ARCH_MULTIPLATFORM
9 - select AUTO_ZRELADDR
14 @@ -751,6 +751,8 @@ source "arch/arm/mach-highbank/Kconfig"
16 source "arch/arm/mach-hisi/Kconfig"
18 +source "arch/arm/mach-hibvt/Kconfig"
20 source "arch/arm/mach-imx/Kconfig"
22 source "arch/arm/mach-integrator/Kconfig"
23 diff --git a/arch/arm/Makefile b/arch/arm/Makefile
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/kernel/linux/patches/linux-5.10/hi3516dv300_patch/
Dhi3516dv300.patch1 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
3 --- a/arch/arm/Kconfig
5 @@ -322,7 +322,7 @@ config ARCH_MULTIPLATFORM
9 - select AUTO_ZRELADDR
14 @@ -650,6 +650,8 @@ source "arch/arm/mach-highbank/Kconfig"
16 source "arch/arm/mach-hisi/Kconfig"
18 +source "arch/arm/mach-hibvt/Kconfig"
20 source "arch/arm/mach-imx/Kconfig"
22 source "arch/arm/mach-integrator/Kconfig"
23 diff --git a/arch/arm/Makefile b/arch/arm/Makefile
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