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Searched +full:dphy +full:- +full:cfg (Results 1 – 25 of 25) sorted by relevance

/kernel/linux/linux-5.10/drivers/phy/cadence/
Dcdns-dphy.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright: 2017-2018 Cadence Design Systems, Inc.
16 #include <linux/phy/phy-mipi-dphy.h>
21 /* DPHY registers */
76 int (*probe)(struct cdns_dphy *dphy);
77 void (*remove)(struct cdns_dphy *dphy);
78 void (*set_psm_div)(struct cdns_dphy *dphy, u8 div);
79 void (*set_clk_lane_cfg)(struct cdns_dphy *dphy,
80 enum cdns_dphy_clk_lane_cfg cfg);
81 void (*set_pll_cfg)(struct cdns_dphy *dphy,
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/kernel/linux/linux-4.19/drivers/gpu/drm/bridge/
Dcdns-dsi.c1 // SPDX-License-Identifier: GPL-2.0
66 #define DATA_LANE_EN(x) BIT((x) - 1)
425 /* DPHY registers */
494 int (*probe)(struct cdns_dphy *dphy);
495 void (*remove)(struct cdns_dphy *dphy);
496 void (*set_psm_div)(struct cdns_dphy *dphy, u8 div);
497 void (*set_clk_lane_cfg)(struct cdns_dphy *dphy,
498 enum cdns_dphy_clk_lane_cfg cfg);
499 void (*set_pll_cfg)(struct cdns_dphy *dphy,
500 const struct cdns_dphy_cfg *cfg);
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Drockchip-mipi-dphy-rx0.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC MIPI RX0 D-PHY Device Tree Bindings
10 - Helen Koike <helen.koike@collabora.com>
11 - Ezequiel Garcia <ezequiel@collabora.com>
14 The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to
19 const: rockchip,rk3399-mipi-dphy-rx0
23 - description: MIPI D-PHY ref clock
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/kernel/linux/linux-5.10/drivers/phy/freescale/
Dphy-fsl-imx8-mipi-dphy.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/clk-provider.h>
19 /* DPHY registers */
47 ((x) < 32) ? 0xe0 | ((x) - 16) : \
48 ((x) < 64) ? 0xc0 | ((x) - 32) : \
49 ((x) < 128) ? 0x80 | ((x) - 64) : \
50 ((x) - 128))
51 #define CN(x) (((x) == 1) ? 0x1f : (((CN_BUF) >> ((x) - 1)) & 0x1f))
52 #define CO(x) ((CO_BUF) >> (8 - (x)) & 0x03)
81 /* DPHY PLL parameters */
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/kernel/linux/linux-5.10/drivers/staging/media/rkisp1/
Drkisp1-isp.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Rockchip ISP1 Driver - ISP Subdevice
13 #include <linux/phy/phy-mipi-dphy.h>
17 #include <media/v4l2-event.h>
19 #include "rkisp1-common.h"
40 * +---------------------------------------------------------+
42 * | +---------------------------------------------------+ |
45 * | | +--------------------------------------------+ | |
48 * | | | +---------------------------------+ | | |
51 * | | | +---------------------------------+ | | |
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Drkisp1-common.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
3 * Rockchip ISP1 Driver - Common definitions
16 #include <media/media-device.h>
17 #include <media/media-entity.h>
18 #include <media/v4l2-ctrls.h>
19 #include <media/v4l2-device.h>
20 #include <media/videobuf2-v4l2.h>
22 #include "rkisp1-regs.h"
23 #include "uapi/rkisp1-config.h"
92 * struct rkisp1_sensor_async - A container for the v4l2_async_subdev to add to the notifier
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/kernel/linux/linux-5.10/drivers/phy/rockchip/
Dphy-rockchip-inno-dsidphy.c1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
11 #include <linux/clk-provider.h>
19 #include <linux/phy/phy-mipi-dphy.h>
213 orig = readl(inno->phy_base + reg); in phy_update_bits()
216 writel(tmp, inno->phy_base + reg); in phy_update_bits()
222 unsigned long prate = clk_get_rate(inno->ref_clk); in inno_dsidphy_pll_calc_rate()
233 * PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2 in inno_dsidphy_pll_calc_rate()
266 delta = abs(fout - tmp); in inno_dsidphy_pll_calc_rate()
281 inno->pll.prediv = best_prediv; in inno_dsidphy_pll_calc_rate()
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Dphy-rockchip-dphy-rx0.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Rockchip MIPI Synopsys DPHY RX0 driver
11 * chromeos-4.4 branch.
14 * Jacob Chen <jacob2.chen@rock-chips.com>
15 * Shunqian Zheng <zhengsq@rock-chips.com>
26 #include <linux/phy/phy-mipi-dphy.h>
65 "dphy-ref",
66 "dphy-cfg",
111 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
163 const struct dphy_reg *reg = &priv->drv_data->regs[index]; in rk_dphy_write_grf()
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/kernel/linux/linux-5.10/drivers/phy/
Dphy-core-mipi-dphy.c1 /* SPDX-License-Identifier: GPL-2.0 */
13 #include <linux/phy/phy-mipi-dphy.h>
18 * Minimum D-PHY timings based on MIPI D-PHY specification. Derived
20 * of the D-PHY specification (v2.1).
25 struct phy_configure_opts_mipi_dphy *cfg) in phy_mipi_dphy_get_default_config() argument
30 if (!cfg) in phy_mipi_dphy_get_default_config()
31 return -EINVAL; in phy_mipi_dphy_get_default_config()
39 cfg->clk_miss = 0; in phy_mipi_dphy_get_default_config()
40 cfg->clk_post = 60000 + 52 * ui; in phy_mipi_dphy_get_default_config()
41 cfg->clk_pre = 8000; in phy_mipi_dphy_get_default_config()
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/kernel/linux/linux-5.10/drivers/gpu/drm/bridge/
Dnwl-dsi.c1 // SPDX-License-Identifier: GPL-2.0+
33 #include "nwl-dsi.h"
35 #define DRV_NAME "nwl-dsi"
85 * 2. Configure DSI Host and DPHY and enable DPHY
136 int ret = dsi->error; in nwl_dsi_clear_error()
138 dsi->error = 0; in nwl_dsi_clear_error()
146 if (dsi->error) in nwl_dsi_write()
149 ret = regmap_write(dsi->regmap, reg, val); in nwl_dsi_write()
151 DRM_DEV_ERROR(dsi->dev, in nwl_dsi_write()
154 dsi->error = ret; in nwl_dsi_write()
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/kernel/linux/linux-5.10/drivers/gpu/drm/sun4i/
Dsun6i_mipi_dsi.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2017-2018 Bootlin
11 #include <linux/crc-ccitt.h>
14 #include <linux/phy/phy-mipi-dphy.h>
293 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_abort()
299 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_commit()
308 return regmap_read_poll_timeout(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_wait_for_completion()
321 regmap_write(dsi->regs, SUN6I_DSI_INST_FUNC_REG(id), in sun6i_dsi_inst_setup()
332 u8 lanes_mask = GENMASK(device->lanes - 1, 0); in sun6i_dsi_inst_init()
359 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_CFG_REG(0), in sun6i_dsi_inst_init()
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/kernel/linux/linux-5.10/drivers/staging/media/imx/
Dimx6-mipi-csi2.c1 // SPDX-License-Identifier: GPL-2.0+
3 * MIPI CSI-2 Receiver Subdev for Freescale i.MX6 SOC.
5 * Copyright (c) 2012-2017 Mentor Graphics Inc.
15 #include <media/v4l2-device.h>
16 #include <media/v4l2-fwnode.h>
17 #include <media/v4l2-mc.h>
18 #include <media/v4l2-subdev.h>
19 #include "imx-media.h"
31 * The default maximum bit-rate per lane in Mbps, if the
57 #define DEVICE_NAME "imx6-mipi-csi2"
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/kernel/linux/linux-4.19/drivers/staging/media/imx/
Dimx6-mipi-csi2.c2 * MIPI CSI-2 Receiver Subdev for Freescale i.MX6 SOC.
4 * Copyright (c) 2012-2017 Mentor Graphics Inc.
19 #include <media/v4l2-device.h>
20 #include <media/v4l2-fwnode.h>
21 #include <media/v4l2-subdev.h>
22 #include "imx-media.h"
34 * The default maximum bit-rate per lane in Mbps, if the
59 #define DEVICE_NAME "imx6-mipi-csi2"
86 * not part of the MIPI CSI-2 core, but its registers fall in the
98 * The required sequence of MIPI CSI-2 startup as specified in the i.MX6
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/kernel/linux/linux-5.10/drivers/staging/media/tegra-video/
Dcsi.c1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <media/v4l2-fwnode.h>
67 struct v4l2_subdev_pad_config *cfg, in csi_enum_bus_code() argument
71 return -ENOIOCTLCMD; in csi_enum_bus_code()
73 if (code->index >= ARRAY_SIZE(tegra_csi_tpg_fmts)) in csi_enum_bus_code()
74 return -EINVAL; in csi_enum_bus_code()
76 code->code = tegra_csi_tpg_fmts[code->index].code; in csi_enum_bus_code()
82 struct v4l2_subdev_pad_config *cfg, in csi_get_format() argument
88 return -ENOIOCTLCMD; in csi_get_format()
90 fmt->format = csi_chan->format; in csi_get_format()
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/kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/phy/
Ddsi_phy_7nm.c2 * SPDX-License-Identifier: GPL-2.0
13 void __iomem *base = phy->base; in dsi_phy_hw_v4_0_is_pll_on()
24 void __iomem *lane_base = phy->lane_base; in dsi_phy_hw_v4_0_config_lpcdrx()
45 void __iomem *lane_base = phy->lane_base; in dsi_phy_hw_v4_0_lane_settings()
47 if (phy->cfg->type == MSM_DSI_PHY_7NM_V4_1) in dsi_phy_hw_v4_0_lane_settings()
79 struct msm_dsi_dphy_timing *timing = &phy->timing; in dsi_7nm_phy_enable()
80 void __iomem *base = phy->base; in dsi_7nm_phy_enable()
89 DRM_DEV_ERROR(&phy->pdev->dev, in dsi_7nm_phy_enable()
90 "%s: D-PHY timing calculation failed\n", __func__); in dsi_7nm_phy_enable()
91 return -EINVAL; in dsi_7nm_phy_enable()
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/kernel/linux/linux-5.10/drivers/media/platform/cadence/
Dcdns-csi2tx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Cadence MIPI-CSI2 TX Controller
5 * Copyright (C) 2017-2019 Cadence Design Systems Inc.
18 #include <media/v4l2-ctrls.h>
19 #include <media/v4l2-device.h>
20 #include <media/v4l2-fwnode.h>
21 #include <media/v4l2-subdev.h>
159 struct v4l2_subdev_pad_config *cfg, in csi2tx_enum_mbus_code() argument
162 if (code->pad || code->index >= ARRAY_SIZE(csi2tx_formats)) in csi2tx_enum_mbus_code()
163 return -EINVAL; in csi2tx_enum_mbus_code()
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/kernel/linux/linux-5.10/drivers/phy/allwinner/
Dphy-sun4i-usb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2014-2015 Hans de Goede <hdegoede@redhat.com>
10 * Modelled after: Samsung S5P/Exynos SoC series MIPI CSIS/DSIM DPHY driver
18 #include <linux/extcon-provider.h>
30 #include <linux/phy/phy-sun4i-usb.h>
127 const struct sun4i_usb_phy_cfg *cfg; member
157 container_of((phy), struct sun4i_usb_phy_data, phys[(phy)->index])
165 iscr = readl(data->base + REG_ISCR); in sun4i_usb_phy0_update_iscr()
168 writel(iscr, data->base + REG_ISCR); in sun4i_usb_phy0_update_iscr()
195 u32 temp, usbc_bit = BIT(phy->index * 2); in sun4i_usb_phy_write()
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/kernel/linux/linux-4.19/drivers/phy/allwinner/
Dphy-sun4i-usb.c4 * Copyright (C) 2014-2015 Hans de Goede <hdegoede@redhat.com>
9 * Modelled after: Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY driver
27 #include <linux/extcon-provider.h>
38 #include <linux/phy/phy-sun4i-usb.h>
134 const struct sun4i_usb_phy_cfg *cfg; member
164 container_of((phy), struct sun4i_usb_phy_data, phys[(phy)->index])
172 iscr = readl(data->base + REG_ISCR); in sun4i_usb_phy0_update_iscr()
175 writel(iscr, data->base + REG_ISCR); in sun4i_usb_phy0_update_iscr()
202 u32 temp, usbc_bit = BIT(phy->index * 2); in sun4i_usb_phy_write()
203 void __iomem *phyctl = phy_data->base + phy_data->cfg->phyctl_offset; in sun4i_usb_phy_write()
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/kernel/linux/linux-4.19/drivers/media/pci/intel/ipu3/
Dipu3-cio2.c1 // SPDX-License-Identifier: GPL-2.0
22 #include <media/v4l2-ctrls.h>
23 #include <media/v4l2-device.h>
24 #include <media/v4l2-event.h>
25 #include <media/v4l2-fwnode.h>
26 #include <media/v4l2-ioctl.h>
27 #include <media/videobuf2-dma-sg.h>
29 #include "ipu3-cio2.h"
64 * cio2_find_format - lookup color format by fourcc or/and media bus code
98 if (cio2->dummy_lop) { in cio2_fbpt_exit_dummy()
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/kernel/linux/linux-5.10/drivers/media/pci/intel/ipu3/
Dipu3-cio2.c1 // SPDX-License-Identifier: GPL-2.0
23 #include <media/v4l2-ctrls.h>
24 #include <media/v4l2-device.h>
25 #include <media/v4l2-event.h>
26 #include <media/v4l2-fwnode.h>
27 #include <media/v4l2-ioctl.h>
28 #include <media/videobuf2-dma-sg.h>
30 #include "ipu3-cio2.h"
65 * cio2_find_format - lookup color format by fourcc or/and media bus code
99 if (cio2->dummy_lop) { in cio2_fbpt_exit_dummy()
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dimx8mq-librem5.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2020 Purism SPC
6 /dts-v1/;
8 #include "dt-bindings/input/input.h"
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include "dt-bindings/pwm/pwm.h"
11 #include "dt-bindings/usb/pd.h"
18 backlight_dsi: backlight-dsi {
19 compatible = "led-backlight";
23 pmic_osc: clock-pmic {
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/kernel/linux/linux-4.19/drivers/media/i2c/smiapp/
Dsmiapp-core.c2 * drivers/media/i2c/smiapp/smiapp-core.c
6 * Copyright (C) 2010--2012 Nokia Corporation
11 * Based on smia-sensor.c by Tuukka Toivonen <tuukkat76@gmail.com>
34 #include <linux/v4l2-mediabus.h>
35 #include <media/v4l2-fwnode.h>
36 #include <media/v4l2-device.h>
46 * smiapp_module_idents - supported camera modules
49 SMIAPP_IDENT_L(0x01, 0x022b, -1, "vs6555"),
50 SMIAPP_IDENT_L(0x01, 0x022e, -1, "vw6558"),
51 SMIAPP_IDENT_L(0x07, 0x7698, -1, "ovm7698"),
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/kernel/linux/linux-5.10/drivers/media/i2c/smiapp/
Dsmiapp-core.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/media/i2c/smiapp/smiapp-core.c
7 * Copyright (C) 2010--2012 Nokia Corporation
12 * Based on smia-sensor.c by Tuukka Toivonen <tuukkat76@gmail.com>
26 #include <linux/v4l2-mediabus.h>
27 #include <media/v4l2-fwnode.h>
28 #include <media/v4l2-device.h>
38 * smiapp_module_idents - supported camera modules
41 SMIAPP_IDENT_L(0x01, 0x022b, -1, "vs6555"),
42 SMIAPP_IDENT_L(0x01, 0x022e, -1, "vw6558"),
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/kernel/linux/linux-5.10/drivers/clk/sprd/
Dsc9863a-clk.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/sprd,sc9863a-clk.h>
26 static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll0_gate, "mpll0-gate", "ext-26m", 0x94,
28 static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll0_gate, "dpll0-gate", "ext-26m", 0x98,
30 static SPRD_PLL_SC_GATE_CLK_FW_NAME(lpll_gate, "lpll-gate", "ext-26m", 0x9c,
32 static SPRD_PLL_SC_GATE_CLK_FW_NAME(gpll_gate, "gpll-gate", "ext-26m", 0xa8,
34 static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll1_gate, "dpll1-gate", "ext-26m", 0x1dc,
36 static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll1_gate, "mpll1-gate", "ext-26m", 0x1e0,
38 static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll2_gate, "mpll2-gate", "ext-26m", 0x1e4,
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/rockchip/
Drk3399.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
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