| /kernel/linux/linux-5.10/drivers/gpu/drm/bridge/adv7511/ |
| D | adv7533.c | 1 // SPDX-License-Identifier: GPL-2.0-only
29 struct mipi_dsi_device *dsi = adv->dsi; in adv7511_dsi_config_timing_gen() local
30 struct drm_display_mode *mode = &adv->curr_mode; in adv7511_dsi_config_timing_gen()
32 u8 clock_div_by_lanes[] = { 6, 4, 3 }; /* 2, 3, 4 lanes */ in adv7511_dsi_config_timing_gen()
34 hsw = mode->hsync_end - mode->hsync_start; in adv7511_dsi_config_timing_gen()
35 hfp = mode->hsync_start - mode->hdisplay; in adv7511_dsi_config_timing_gen()
36 hbp = mode->htotal - mode->hsync_end; in adv7511_dsi_config_timing_gen()
37 vsw = mode->vsync_end - mode->vsync_start; in adv7511_dsi_config_timing_gen()
38 vfp = mode->vsync_start - mode->vdisplay; in adv7511_dsi_config_timing_gen()
39 vbp = mode->vtotal - mode->vsync_end; in adv7511_dsi_config_timing_gen()
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| /kernel/linux/linux-4.19/drivers/gpu/drm/bridge/adv7511/ |
| D | adv7533.c | 37 struct mipi_dsi_device *dsi = adv->dsi; in adv7511_dsi_config_timing_gen() local
38 struct drm_display_mode *mode = &adv->curr_mode; in adv7511_dsi_config_timing_gen()
40 u8 clock_div_by_lanes[] = { 6, 4, 3 }; /* 2, 3, 4 lanes */ in adv7511_dsi_config_timing_gen()
42 hsw = mode->hsync_end - mode->hsync_start; in adv7511_dsi_config_timing_gen()
43 hfp = mode->hsync_start - mode->hdisplay; in adv7511_dsi_config_timing_gen()
44 hbp = mode->htotal - mode->hsync_end; in adv7511_dsi_config_timing_gen()
45 vsw = mode->vsync_end - mode->vsync_start; in adv7511_dsi_config_timing_gen()
46 vfp = mode->vsync_start - mode->vdisplay; in adv7511_dsi_config_timing_gen()
47 vbp = mode->vtotal - mode->vsync_end; in adv7511_dsi_config_timing_gen()
50 regmap_write(adv->regmap_cec, 0x16, in adv7511_dsi_config_timing_gen()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/bridge/ |
| D | nwl-dsi.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * i.MX8 NWL MIPI DSI host driver
33 #include "nwl-dsi.h"
35 #define DRV_NAME "nwl-dsi"
83 * The DSI host controller needs this reset sequence according to NWL:
84 * 1. Deassert pclk reset to get access to DSI regs
85 * 2. Configure DSI Host and DPHY and enable DPHY
87 * 4. Send DSI cmds to configure peripheral (handled by panel drv)
89 * DSI data
91 * TODO: Since panel_bridges do their DSI setup in enable we
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| D | cdns-dsi.c | 1 // SPDX-License-Identifier: GPL-2.0
27 #include <linux/phy/phy-mipi-dphy.h>
71 #define DATA_LANE_EN(x) BIT((x) - 1)
488 return mode->hsync_start - mode->hdisplay; in mode_to_dpi_hfp()
490 return mode->crtc_hsync_start - mode->crtc_hdisplay; in mode_to_dpi_hfp()
502 dsi_timing -= dsi_pkt_overhead; in dpi_to_dsi_timing()
507 static int cdns_dsi_mode2cfg(struct cdns_dsi *dsi, in cdns_dsi_mode2cfg() argument
512 struct cdns_dsi_output *output = &dsi->output; in cdns_dsi_mode2cfg()
519 if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) in cdns_dsi_mode2cfg()
522 bpp = mipi_dsi_pixel_format_to_bpp(output->dev->format); in cdns_dsi_mode2cfg()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/bridge/synopsys/ |
| D | dw-mipi-dsi.c | 1 // SPDX-License-Identifier: GPL-2.0+
7 * This generic Synopsys DesignWare MIPI DSI host driver is based on the
8 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
193 #define N_LANES(n) (((n) - 1) & 0x3)
226 #define VPG_DEFS(name, dsi) \ argument
227 ((void __force *)&((*dsi).vpg_defs.name))
229 #define REGISTER(name, mask, dsi) \ argument
230 { #name, VPG_DEFS(name, dsi), mask, dsi }
236 struct dw_mipi_dsi *dsi; member
251 u32 lanes; member
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| /kernel/linux/linux-5.10/drivers/gpu/drm/hisilicon/kirin/ |
| D | dw_drm_dsi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * DesignWare MIPI DSI Host Controller v1.02 driver
6 * Copyright (c) 2014-2016 Hisilicon Limited.
90 u32 lanes; member
97 struct dw_dsi dsi; member
151 phy->pll_vco_750M = dphy_range_info[i].pll_vco_750M; in dsi_calc_phy_rate()
152 phy->hstx_ckg_sel = dphy_range_info[i].hstx_ckg_sel; in dsi_calc_phy_rate()
154 if (phy->hstx_ckg_sel <= 7 && in dsi_calc_phy_rate()
155 phy->hstx_ckg_sel >= 4) in dsi_calc_phy_rate()
156 q_pll = 0x10 >> (7 - phy->hstx_ckg_sel); in dsi_calc_phy_rate()
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| /kernel/linux/linux-4.19/drivers/gpu/drm/hisilicon/kirin/ |
| D | dw_drm_dsi.c | 2 * DesignWare MIPI DSI Host Controller v1.02 driver
5 * Copyright (c) 2014-2016 Hisilicon Limited.
88 u32 lanes; member
95 struct dw_dsi dsi; member
149 phy->pll_vco_750M = dphy_range_info[i].pll_vco_750M; in dsi_calc_phy_rate()
150 phy->hstx_ckg_sel = dphy_range_info[i].hstx_ckg_sel; in dsi_calc_phy_rate()
152 if (phy->hstx_ckg_sel <= 7 && in dsi_calc_phy_rate()
153 phy->hstx_ckg_sel >= 4) in dsi_calc_phy_rate()
154 q_pll = 0x10 >> (7 - phy->hstx_ckg_sel); in dsi_calc_phy_rate()
188 phy->pll_fbd_p = 0; in dsi_calc_phy_rate()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/tegra/ |
| D | dsi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
29 #include "dsi.h"
30 #include "mipi-phy.h"
40 unsigned int lanes; member
71 unsigned int lanes; member
81 /* for ganged-mode support */
102 static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi) in tegra_dsi_get_state() argument
104 return to_dsi_state(dsi->output.connector.state); in tegra_dsi_get_state()
107 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset) in tegra_dsi_readl() argument
109 u32 value = readl(dsi->regs + (offset << 2)); in tegra_dsi_readl()
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| /kernel/linux/linux-4.19/drivers/gpu/drm/tegra/ |
| D | dsi.c | 29 #include "dsi.h"
30 #include "mipi-phy.h"
40 unsigned int lanes; member
71 unsigned int lanes; member
81 /* for ganged-mode support */
102 static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi) in tegra_dsi_get_state() argument
104 return to_dsi_state(dsi->output.connector.state); in tegra_dsi_get_state()
107 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset) in tegra_dsi_readl() argument
109 u32 value = readl(dsi->regs + (offset << 2)); in tegra_dsi_readl()
111 trace_dsi_readl(dsi->dev, offset, value); in tegra_dsi_readl()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/msm/ |
| D | dsi.txt | 1 Qualcomm Technologies Inc. adreno/snapdragon DSI output
3 DSI Controller:
5 - compatible:
6 * "qcom,mdss-dsi-ctrl"
7 - reg: Physical base address and length of the registers of controller
8 - reg-names: The names of register regions. The following regions are required:
10 - interrupts: The interrupt signal from the DSI block.
11 - power-domains: Should be <&mmcc MDSS_GDSC>.
12 - clocks: Phandles to device clocks.
13 - clock-names: the following clocks are required:
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/display/msm/ |
| D | dsi.txt | 1 Qualcomm Technologies Inc. adreno/snapdragon DSI output
3 DSI Controller:
5 - compatible:
6 * "qcom,mdss-dsi-ctrl"
7 - reg: Physical base address and length of the registers of controller
8 - reg-names: The names of register regions. The following regions are required:
10 - interrupts: The interrupt signal from the DSI block.
11 - power-domains: Should be <&mmcc MDSS_GDSC>.
12 - clocks: Phandles to device clocks.
13 - clock-names: the following clocks are required:
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| /kernel/linux/linux-5.10/drivers/gpu/drm/vc4/ |
| D | vc4_dsi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 * BCM2835 contains two DSI modules, DSI0 and DSI1. DSI0 is a
10 * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI
16 * This driver has been tested for DSI1 video-mode display only
21 #include <linux/clk-provider.h>
25 #include <linux/dma-mapping.h>
146 * of going to LP-STOP.
149 /* Transmit blanking packet only during vblank, instead of allowing LP-STOP. */
151 /* Transmit blanking packet only during HFP, instead of allowing LP-STOP. */
153 /* Transmit blanking packet only during HBP, instead of allowing LP-STOP. */
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| /kernel/linux/linux-4.19/drivers/gpu/drm/vc4/ |
| D | vc4_dsi.c | 20 * BCM2835 contains two DSI modules, DSI0 and DSI1. DSI0 is a
21 * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI
27 * This driver has been tested for DSI1 video-mode display only
39 #include <linux/clk-provider.h>
151 * of going to LP-STOP.
154 /* Transmit blanking packet only during vblank, instead of allowing LP-STOP. */
156 /* Transmit blanking packet only during HFP, instead of allowing LP-STOP. */
158 /* Transmit blanking packet only during HBP, instead of allowing LP-STOP. */
501 /* General DSI hardware state. */
519 /* DSI channel for the panel we're connected to. */
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/ti/ |
| D | ti,omap5-dss.txt | 4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap5-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
18 - DISPC
21 - DSS Submodules: RFBI, DSI, HDMI
22 - Video port for DPI output
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| D | ti,omap4-dss.txt | 4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap4-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
18 - DISPC
21 - DSS Submodules: RFBI, VENC, DSI, HDMI
22 - Video port for DPI output
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/display/ti/ |
| D | ti,omap5-dss.txt | 4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap5-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
18 - DISPC
21 - DSS Submodules: RFBI, DSI, HDMI
22 - Video port for DPI output
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| D | ti,omap4-dss.txt | 4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap4-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
18 - DISPC
21 - DSS Submodules: RFBI, VENC, DSI, HDMI
22 - Video port for DPI output
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| D | ti,omap3-dss.txt | 4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap3-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
18 - Video ports:
19 - Port 0: DPI output
20 - Port 1: SDI output
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/panel/ |
| D | raydium,rm67191.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Raydium RM67171 OLED LCD panel with MIPI-DSI protocol
10 - Robert Chiras <robert.chiras@nxp.com>
13 - $ref: panel-common.yaml#
21 reset-gpios: true
22 width-mm: true
23 height-mm: true
25 dsi-lanes:
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| /kernel/linux/linux-4.19/drivers/gpu/drm/bridge/synopsys/ |
| D | dw-mipi-dsi.c | 1 // SPDX-License-Identifier: GPL-2.0+
7 * This generic Synopsys DesignWare MIPI DSI host driver is based on the
8 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
186 #define N_LANES(n) (((n) - 1) & 0x3)
229 u32 lanes; member
259 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val) in dsi_write() argument
261 writel(val, dsi->base + reg); in dsi_write()
264 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) in dsi_read() argument
266 return readl(dsi->base + reg); in dsi_read()
272 struct dw_mipi_dsi *dsi = host_to_dsi(host); in dw_mipi_dsi_host_attach() local
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| /kernel/linux/linux-4.19/drivers/gpu/drm/bridge/ |
| D | cdns-dsi.c | 1 // SPDX-License-Identifier: GPL-2.0
66 #define DATA_LANE_EN(x) BIT((x) - 1)
558 unsigned long pll_ref_hz = clk_get_rate(dphy->pll_ref_clk); in cdns_dsi_get_dphy_pll_cfg()
562 cfg->nlanes = dsi_nlanes; in cdns_dsi_get_dphy_pll_cfg()
565 return -EINVAL; in cdns_dsi_get_dphy_pll_cfg()
567 cfg->pll_ipdiv = 1; in cdns_dsi_get_dphy_pll_cfg()
569 cfg->pll_ipdiv = 2; in cdns_dsi_get_dphy_pll_cfg()
571 cfg->pll_ipdiv = 4; in cdns_dsi_get_dphy_pll_cfg()
573 cfg->pll_ipdiv = 8; in cdns_dsi_get_dphy_pll_cfg()
576 * Make sure DSI htotal is aligned on a lane boundary when calculating in cdns_dsi_get_dphy_pll_cfg()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/panel/ |
| D | panel-sitronix-st7703.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * - Rocktech jh057n00900 5.5" MIPI-DSI panel
13 #include <linux/media-bus-format.h>
26 #define DRV_NAME "panel-sitronix-st7703"
28 /* Manufacturer specific Commands send via DSI */
65 unsigned int lanes; member
76 #define dsi_generic_write_seq(dsi, seq...) do { \ argument
79 ret = mipi_dsi_generic_write(dsi, d, ARRAY_SIZE(d)); \
86 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); in jh057n_init_sequence() local
93 dsi_generic_write_seq(dsi, ST7703_CMD_SETEXTC, in jh057n_init_sequence()
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| /kernel/linux/linux-4.19/drivers/gpu/drm/sun4i/ |
| D | sun6i_mipi_dphy.c | 1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2017-2018 Bootlin
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
18 #define SUN6I_DPHY_GCTL_LANE_NUM(n) ((((n) - 1) & 3) << 4)
84 int sun6i_dphy_init(struct sun6i_dphy *dphy, unsigned int lanes) in sun6i_dphy_init() argument
86 reset_control_deassert(dphy->reset); in sun6i_dphy_init()
87 clk_prepare_enable(dphy->mod_clk); in sun6i_dphy_init()
88 clk_set_rate_exclusive(dphy->mod_clk, 150000000); in sun6i_dphy_init()
90 regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG, in sun6i_dphy_init()
93 regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME0_REG, in sun6i_dphy_init()
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| /kernel/linux/linux-4.19/include/drm/ |
| D | drm_mipi_dsi.h | 2 * MIPI DSI Bus
4 * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd.
26 * struct mipi_dsi_msg - read/write DSI buffer
51 * struct mipi_dsi_packet - represents a MIPI DSI packet in protocol format
69 * struct mipi_dsi_host_ops - DSI bus operations
70 * @attach: attach DSI device to DSI host
71 * @detach: detach DSI device from DSI host
72 * @transfer: transmit a DSI packet
74 * DSI packets transmitted by .transfer() are passed in as mipi_dsi_msg
82 * Note that typically DSI packet transmission is atomic, so the .transfer()
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| /kernel/linux/linux-5.10/include/drm/ |
| D | drm_mipi_dsi.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * MIPI DSI Bus
5 * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd.
24 * struct mipi_dsi_msg - read/write DSI buffer
49 * struct mipi_dsi_packet - represents a MIPI DSI packet in protocol format
67 * struct mipi_dsi_host_ops - DSI bus operations
68 * @attach: attach DSI device to DSI host
69 * @detach: detach DSI device from DSI host
70 * @transfer: transmit a DSI packet
72 * DSI packets transmitted by .transfer() are passed in as mipi_dsi_msg
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