| /kernel/linux/linux-5.10/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac-meson8b.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Amlogic Meson8b, Meson8m2 and GXBB DWMAC glue layer
10 #include <linux/clk-provider.h>
43 #define PRG_ETH0_CLK_M250_DIV_WIDTH 3
51 * internal sampling) or enable (= 1) the internal logic for RXEN and RXD[3:0]
55 /* Controls whether the RXEN and RXD[3:0] signals should be aligned with the
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
62 * delay (= the counter value) when to start sampling RXEN and RXD[3:0].
65 /* Adjusts the skew between each bit of RXEN and RXD[3:0]. If a signal has a
66 * large input delay, the bit for that signal (RXEN = bit 0, RXD[3] = bit 1,
[all …]
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| D | dwmac-sti.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer
5 * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited
44 * ------------------------------------------------
47 * ------------------------------------------------
49 *| | clk-125/txclk | txclk |
50 * ------------------------------------------------
52 *| | clk-125/txclk | clkgen |
54 * ------------------------------------------------
56 *| | |clkgen/phyclk-in |
[all …]
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| D | dwmac-oxnas.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Oxford Semiconductor OXNAS DWMAC glue layer
36 #define DWMAC_AUTO_TX_SOURCE 3
59 struct oxnas_dwmac *dwmac = priv; in oxnas_dwmac_init() local
64 ret = device_reset(dwmac->dev); in oxnas_dwmac_init()
68 ret = clk_prepare_enable(dwmac->clk); in oxnas_dwmac_init()
72 ret = regmap_read(dwmac->regmap, OXNAS_DWMAC_CTRL_REGOFFSET, &value); in oxnas_dwmac_init()
74 clk_disable_unprepare(dwmac->clk); in oxnas_dwmac_init()
91 regmap_write(dwmac->regmap, OXNAS_DWMAC_CTRL_REGOFFSET, value); in oxnas_dwmac_init()
98 regmap_write(dwmac->regmap, OXNAS_DWMAC_DELAY_REGOFFSET, value); in oxnas_dwmac_init()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | amlogic,meson-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Amlogic Meson DWMAC Ethernet controller
11 - Neil Armstrong <narmstrong@baylibre.com>
12 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
14 # We need a select here so we don't match all nodes with 'snps,dwmac'
20 - amlogic,meson6-dwmac
21 - amlogic,meson8b-dwmac
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| D | stm32-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/net/stm32-dwmac.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: STMicroelectronics STM32 / MCU DWMAC glue layer controller
11 - Alexandre Torgue <alexandre.torgue@st.com>
12 - Christophe Roullier <christophe.roullier@st.com>
17 # We need a select here so we don't match all nodes with 'snps,dwmac'
23 - st,stm32-dwmac
24 - st,stm32mp1-dwmac
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| D | snps,dwmac.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/snps,dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.50a
25 - snps,dwmac-3.610
[all …]
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| D | intel,dwmac-plat.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel DWMAC glue layer Device Tree Bindings
10 - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
17 - intel,keembay-dwmac
19 - compatible
22 - $ref: "snps,dwmac.yaml#"
27 - items:
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| /kernel/linux/linux-4.19/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac-meson8b.c | 2 * Amlogic Meson8b, Meson8m2 and GXBB DWMAC glue layer
15 #include <linux/clk-provider.h>
46 #define PRG_ETH0_CLK_M250_DIV_WIDTH 3
58 int (*set_phy_mode)(struct meson8b_dwmac *dwmac);
78 static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg, in meson8b_dwmac_mask_bits() argument
83 data = readl(dwmac->regs + reg); in meson8b_dwmac_mask_bits()
87 writel(data, dwmac->regs + reg); in meson8b_dwmac_mask_bits()
90 static struct clk *meson8b_dwmac_register_clk(struct meson8b_dwmac *dwmac, in meson8b_dwmac_register_clk() argument
100 snprintf(clk_name, sizeof(clk_name), "%s#%s", dev_name(dwmac->dev), in meson8b_dwmac_register_clk()
109 hw->init = &init; in meson8b_dwmac_register_clk()
[all …]
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| D | dwmac-sti.c | 2 * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer
4 * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited
48 * ------------------------------------------------
51 * ------------------------------------------------
53 *| | clk-125/txclk | txclk |
54 * ------------------------------------------------
56 *| | clk-125/txclk | clkgen |
58 * ------------------------------------------------
60 *| | |clkgen/phyclk-in |
61 * ------------------------------------------------
[all …]
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| D | dwmac-oxnas.c | 2 * Oxford Semiconductor OXNAS DWMAC glue layer
42 #define DWMAC_AUTO_TX_SOURCE 3
65 struct oxnas_dwmac *dwmac = priv; in oxnas_dwmac_init() local
70 ret = device_reset(dwmac->dev); in oxnas_dwmac_init()
74 ret = clk_prepare_enable(dwmac->clk); in oxnas_dwmac_init()
78 ret = regmap_read(dwmac->regmap, OXNAS_DWMAC_CTRL_REGOFFSET, &value); in oxnas_dwmac_init()
80 clk_disable_unprepare(dwmac->clk); in oxnas_dwmac_init()
97 regmap_write(dwmac->regmap, OXNAS_DWMAC_CTRL_REGOFFSET, value); in oxnas_dwmac_init()
104 regmap_write(dwmac->regmap, OXNAS_DWMAC_DELAY_REGOFFSET, value); in oxnas_dwmac_init()
111 struct oxnas_dwmac *dwmac = priv; in oxnas_dwmac_exit() local
[all …]
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| /kernel/linux/linux-4.19/Documentation/networking/ |
| D | stmmac.txt | 3 Copyright (C) 2007-2015 STMicroelectronics Ltd
6 This is the driver for the MAC 10/100/1000 on-chip Ethernet controllers
22 Device Drivers ---> Network device support ---> Ethernet (1000 Mbit) --->
39 3) Command line options
50 net_device structure, enabling the scatter-gather feature. This is true on
62 The incoming packets are stored, by the DMA, in a list of pre-allocated socket
63 buffers in order to avoid the memcpy (zero-copy).
68 New chips have an HW RX-Watchdog used for this mitigation.
80 and linked-list(CHAINED) mode. In RING each descriptor points to two
101 # ethtool -S ethX
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| /kernel/linux/linux-4.19/arch/arm64/boot/dts/altera/ |
| D | socfpga_stratix10.dtsi | 17 /dts-v1/;
18 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
19 #include <dt-bindings/gpio/gpio.h>
20 #include <dt-bindings/clock/stratix10-clock.h>
23 compatible = "altr,socfpga-stratix10";
24 #address-cells = <2>;
25 #size-cells = <2>;
28 #address-cells = <1>;
29 #size-cells = <0>;
32 compatible = "arm,cortex-a53", "arm,armv8";
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/net/ |
| D | stmmac.txt | 4 - compatible: Should be "snps,dwmac-<ip_version>", "snps,dwmac" or
5 "snps,dwxgmac-<ip_version>", "snps,dwxgmac".
6 For backwards compatibility: "st,spear600-gmac" is also supported.
7 - reg: Address and length of the register set for the device
8 - interrupts: Should contain the STMMAC interrupts
9 - interrupt-names: Should contain a list of interrupt names corresponding to
12 - "macirq" (combined signal for various interrupt events)
13 - "eth_wake_irq" (the interrupt to manage the remote wake-up packet detection)
14 - "eth_lpi" (the interrupt that occurs when Rx exits the LPI state)
15 - phy-mode: See ethernet.txt file in the same directory.
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/intel/ |
| D | socfpga_agilex.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/agilex-clock.h>
12 compatible = "intel,socfpga-agilex";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/altera/ |
| D | socfpga_stratix10.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | meson8b.dtsi | 5 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/clock/meson8b-clkc.h>
48 #include <dt-bindings/gpio/meson8b-gpio.h>
49 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
50 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
55 #address-cells = <1>;
56 #size-cells = <0>;
60 compatible = "arm,cortex-a5";
61 next-level-cache = <&L2>;
63 enable-method = "amlogic,meson8b-smp";
[all …]
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| D | artpec6-devboard.dts | 2 * Axis ARTPEC-6 development board.
9 /dts-v1/;
13 model = "ARTPEC-6 development board";
14 compatible = "axis,artpec6-dev-board", "axis,artpec6";
24 stdout-path = "serial3:115200n8";
56 phy-handle = <&phy1>;
57 phy-mode = "gmii";
60 #address-cells = <0x1>;
61 #size-cells = <0x0>;
62 compatible = "snps,dwmac-mdio";
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| D | socfpga_arria10.dtsi | 17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
21 #address-cells = <1>;
22 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
27 enable-method = "altr,socfpga-a10-smp";
30 compatible = "arm,cortex-a9";
33 next-level-cache = <&L2>;
36 compatible = "arm,cortex-a9";
[all …]
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| D | rk3228-evb.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
9 compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
16 vcc_phy: vcc-phy-regulator {
17 compatible = "regulator-fixed";
18 enable-active-high;
19 regulator-name = "vcc_phy";
20 regulator-min-microvolt = <1800000>;
21 regulator-max-microvolt = <1800000>;
22 regulator-always-on;
[all …]
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| D | ox820.dtsi | 2 * ox820.dtsi - Device tree file for Oxford Semiconductor OX820 SoC
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/oxsemi,ox820.h>
12 #include <dt-bindings/reset/oxsemi,ox820.h>
18 #address-cells = <1>;
19 #size-cells = <0>;
20 enable-method = "oxsemi,ox820-smp";
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 clock-frequency = <25000000>;
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | artpec6-devboard.dts | 2 * Axis ARTPEC-6 development board.
9 /dts-v1/;
13 model = "ARTPEC-6 development board";
14 compatible = "axis,artpec6-dev-board", "axis,artpec6";
24 stdout-path = "serial3:115200n8";
56 phy-handle = <&phy1>;
57 phy-mode = "gmii";
60 #address-cells = <0x1>;
61 #size-cells = <0x0>;
62 compatible = "snps,dwmac-mdio";
[all …]
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| D | rk3228-evb.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
9 compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
16 vcc_phy: vcc-phy-regulator {
17 compatible = "regulator-fixed";
18 enable-active-high;
19 regulator-name = "vcc_phy";
20 regulator-min-microvolt = <1800000>;
21 regulator-max-microvolt = <1800000>;
22 regulator-always-on;
[all …]
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| D | ox820.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ox820.dtsi - Device tree file for Oxford Semiconductor OX820 SoC
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/oxsemi,ox820.h>
10 #include <dt-bindings/reset/oxsemi,ox820.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
20 enable-method = "oxsemi,ox820-smp";
[all …]
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| /kernel/linux/linux-4.19/arch/arc/boot/dts/ |
| D | hsdk.dts | 12 /dts-v1/;
14 #include <dt-bindings/net/ti-dp83867.h>
15 #include <dt-bindings/reset/snps,hsdk-reset.h>
21 #address-cells = <1>;
22 #size-cells = <1>;
25 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
33 #address-cells = <1>;
34 #size-cells = <0>;
57 cpu@3 {
60 reg = <3>;
[all …]
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| /kernel/linux/linux-5.10/arch/arc/boot/dts/ |
| D | abilis_tb10x.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
12 compatible = "abilis,arc-tb10x";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
28 compatible = "snps,arc-timer";
29 interrupts = <3>;
30 interrupt-parent = <&intc>;
36 compatible = "snps,arc-timer";
[all …]
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