Home
last modified time | relevance | path

Searched +full:emc +full:- +full:mode +full:- +full:1 (Results 1 – 25 of 88) sorted by relevance

1234

/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dtegra124-nyan-blaze-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 emc-timings-1 {
5 nvidia,ram-code = <1>;
7 timing-12750000 {
8 clock-frequency = <12750000>;
9 nvidia,parent-clock-frequency = <408000000>;
11 clock-names = "emc-parent";
13 timing-20400000 {
14 clock-frequency = <20400000>;
15 nvidia,parent-clock-frequency = <408000000>;
[all …]
Dtegra124-nyan-big-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 emc-timings-1 {
5 nvidia,ram-code = <1>;
7 timing-12750000 {
8 clock-frequency = <12750000>;
9 nvidia,parent-clock-frequency = <408000000>;
11 clock-names = "emc-parent";
13 timing-20400000 {
14 clock-frequency = <20400000>;
15 nvidia,parent-clock-frequency = <408000000>;
[all …]
Dtegra124-apalis-emc.dtsi4 * This file is dual-licensed: you can use it either under the terms
44 emc-timings-1 {
45 nvidia,ram-code = <1>;
47 timing-12750000 {
48 clock-frequency = <12750000>;
49 nvidia,parent-clock-frequency = <408000000>;
51 clock-names = "emc-parent";
53 timing-20400000 {
54 clock-frequency = <20400000>;
55 nvidia,parent-clock-frequency = <408000000>;
[all …]
Dtegra124-jetson-tk1-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 emc-timings-3 {
5 nvidia,ram-code = <3>;
7 timing-12750000 {
8 clock-frequency = <12750000>;
9 nvidia,parent-clock-frequency = <408000000>;
11 clock-names = "emc-parent";
13 timing-20400000 {
14 clock-frequency = <20400000>;
15 nvidia,parent-clock-frequency = <408000000>;
[all …]
Dlpc4350-hitex-eval.dts9 * Released under the terms of 3-clause BSD License
13 /dts-v1/;
18 #include "dt-bindings/input/input.h"
19 #include "dt-bindings/gpio/gpio.h"
23 compatible = "hitex,lpc4350-eval-board", "nxp,lpc4350";
33 stdout-path = &uart0;
42 compatible = "gpio-keys-polled";
43 #address-cells = <1>;
44 #size-cells = <0>;
45 poll-interval = <100>;
[all …]
Dlpc4357-ea4357-devkit.dts9 * Released under the terms of 3-clause BSD License
13 /dts-v1/;
18 #include "dt-bindings/input/input.h"
19 #include "dt-bindings/gpio/gpio.h"
23 compatible = "ea,lpc4357-developers-kit", "nxp,lpc4357", "nxp,lpc4350";
33 stdout-path = &uart0;
42 compatible = "regulator-fixed";
43 regulator-name = "3v3-supply";
44 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dtegra124-nyan-blaze-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 emc-timings-1 {
5 nvidia,ram-code = <1>;
7 timing-12750000 {
8 clock-frequency = <12750000>;
9 nvidia,parent-clock-frequency = <408000000>;
11 clock-names = "emc-parent";
13 timing-20400000 {
14 clock-frequency = <20400000>;
15 nvidia,parent-clock-frequency = <408000000>;
[all …]
Dtegra124-apalis-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Copyright 2016-2019 Toradex AG
9 emc-timings-1 {
10 nvidia,ram-code = <1>;
12 timing-12750000 {
13 clock-frequency = <12750000>;
14 nvidia,parent-clock-frequency = <408000000>;
16 clock-names = "emc-parent";
18 timing-20400000 {
19 clock-frequency = <20400000>;
[all …]
Dtegra124-jetson-tk1-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 emc-timings-3 {
5 nvidia,ram-code = <3>;
7 timing-12750000 {
8 clock-frequency = <12750000>;
9 nvidia,parent-clock-frequency = <408000000>;
11 clock-names = "emc-parent";
13 timing-20400000 {
14 clock-frequency = <20400000>;
15 nvidia,parent-clock-frequency = <408000000>;
[all …]
Dtegra124-nyan-big-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 nvidia,long-ram-code;
8 emc-timings-1 {
9 nvidia,ram-code = <1>;
11 timing-12750000 {
12 clock-frequency = <12750000>;
13 nvidia,parent-clock-frequency = <408000000>;
15 clock-names = "emc-parent";
17 timing-20400000 {
18 clock-frequency = <20400000>;
[all …]
Dtegra30-asus-nexus7-grouper-memory-timings.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 memory-controller@7000f000 {
5 emc-timings-0 {
6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
8 timing-25500000 {
9 clock-frequency = <25500000>;
11 nvidia,emem-configuration = <
33 timing-51000000 {
34 clock-frequency = <51000000>;
36 nvidia,emem-configuration = <
[all …]
Dtegra30-asus-nexus7-tilapia-memory-timings.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "tegra30-asus-nexus7-grouper-memory-timings.dtsi"
12 memory-controller@7000f400 {
13 emc-timings-0 {
14 timing-667000000 {
15 clock-frequency = <667000000>;
17 nvidia,emc-auto-cal-interval = <0x001fffff>;
18 nvidia,emc-mode-1 = <0x80100002>;
19 nvidia,emc-mode-2 = <0x80200018>;
20 nvidia,emc-mode-reset = <0x80000b71>;
[all …]
Dlpc4350-hitex-eval.dts9 * Released under the terms of 3-clause BSD License
13 /dts-v1/;
18 #include "dt-bindings/input/input.h"
19 #include "dt-bindings/gpio/gpio.h"
23 compatible = "hitex,lpc4350-eval-board", "nxp,lpc4350";
33 stdout-path = &uart0;
42 compatible = "gpio-keys-polled";
43 poll-interval = <100>;
97 compatible = "gpio-leds";
102 linux,default-trigger = "heartbeat";
[all …]
Dtegra20-acer-a500-picasso.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra20-cpu-opp.dtsi"
10 #include "tegra20-cpu-opp-microvolt.dtsi"
31 * pre-existing /chosen node to be available to insert the
40 reserved-memory {
41 #address-cells = <1>;
[all …]
Dlpc4357-myd-lpc4357.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * MYIR Tech MYD-LPC4357 Development Board with 800x480 7" TFT panel
5 * Copyright (C) 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
8 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
17 compatible = "myir,myd-lpc4357", "nxp,lpc4357";
20 stdout-path = "serial3:115200n8";
29 compatible = "gpio-leds";
30 pinctrl-names = "default";
31 pinctrl-0 = <&led_pins>;
[all …]
Dlpc4357-ea4357-devkit.dts9 * Released under the terms of 3-clause BSD License
13 /dts-v1/;
18 #include "dt-bindings/input/input.h"
19 #include "dt-bindings/gpio/gpio.h"
23 compatible = "ea,lpc4357-developers-kit", "nxp,lpc4357", "nxp,lpc4350";
33 stdout-path = &uart0;
42 compatible = "regulator-fixed";
43 regulator-name = "3v3-supply";
44 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>;
[all …]
Dtegra20-colibri.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 * Compatible for Revisions Colibri T20 256MB V1.1B, V1.2A;
7 * Colibri T20 256MB IT V1.2A; Colibri T20 512MB V1.1C, V1.2A;
22 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
23 nvidia,hpd-gpio =
25 pll-supply = <&reg_1v8_avdd_hdmi_pll>;
26 vdd-supply = <&reg_3v3_avdd_hdmi>;
31 pinctrl-names = "default";
32 pinctrl-0 = <&state_default>;
35 /* Analogue Audio AC97 to WM9712 (On-module) */
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra30-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The EMC interfaces with the off-chip SDRAM to service the request stream
16 sent from Memory Controller. The EMC also has various performance-affecting
18 settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
[all …]
Dnvidia,tegra124-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The EMC interfaces with the off-chip SDRAM to service the request stream
19 const: nvidia,tegra124-emc
22 maxItems: 1
26 - description: external memory clock
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra124-emc.txt1 NVIDIA Tegra124 SoC EMC (external memory controller)
5 - compatible : Should be "nvidia,tegra124-emc".
6 - reg : physical base address and length of the controller's registers.
7 - nvidia,memory-controller : phandle of the MC driver.
9 The node should contain a "emc-timings" subnode for each supported RAM type
13 Required properties for "emc-timings" nodes :
14 - nvidia,ram-code : Should contain the value of RAM_CODE this timing set is
17 Each "emc-timings" node should contain a "timing" subnode for every supported
18 EMC clock rate. The "timing" subnodes should have the clock rate in Hz as
22 - clock-frequency : Should contain the memory clock rate in Hz.
[all …]
/kernel/linux/linux-5.10/drivers/memory/tegra/
Dtegra30-emc.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
6 * Copyright (C) 2011-2014 NVIDIA Corporation
9 * Copyright (C) 2019 GRATE-DRIVER project
151 ((num) > 1 ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
161 #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1)
192 (((num) > 1 ? 0 : 2) | EMC_REFCTRL_ENABLE)
193 #define EMC_REFCTRL_DISABLE_ALL(num) ((num) > 1 ? 0 : 2)
199 #define EMC_CLKCHANGE_PD_ENABLE BIT(1)
222 [1] = EMC_RFC,
[all …]
Dtegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
21 #include <soc/tegra/emc.h>
264 #define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD BIT(1)
274 #define EMC_REFCTRL_DEV_SEL(n) (((n > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)
275 #define EMC_DRAM_DEV_SEL(n) ((n > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
282 DRAM_TYPE_DDR1 = 1,
488 static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value, in emc_ccfifo_writel() argument
491 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()
492 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel()
[all …]
Dtegra20-emc.c1 // SPDX-License-Identifier: GPL-2.0
77 #define EMC_CLKCHANGE_PD_ENABLE BIT(1)
86 #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1)
163 struct tegra_emc *emc = data; in tegra_emc_isr() local
167 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
173 dev_err_ratelimited(emc->dev, in tegra_emc_isr()
177 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
182 static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc, in tegra_emc_find_timing() argument
188 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_find_timing()
189 if (emc->timings[i].rate >= rate) { in tegra_emc_find_timing()
[all …]
Dtegra210-emc-cc-r21021.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
14 #include "tegra210-emc.h"
15 #include "tegra210-mc.h"
20 #define INFO (1 << 0)
21 #define STEPS (1 << 1)
22 #define SUB_STEPS (1 << 2)
23 #define PRELOCK (1 << 3)
24 #define PRELOCK_STEPS (1 << 4)
25 #define ACTIVE_EN (1 << 5)
[all …]
/kernel/linux/linux-4.19/drivers/memory/tegra/
Dtegra124-emc.c18 #include <linux/clk-provider.h>
29 #include <soc/tegra/emc.h>
272 #define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD BIT(1)
277 #define DRAM_DEV_SEL_1 (1 << 30)
282 #define EMC_REFCTRL_DEV_SEL(n) (((n > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)
283 #define EMC_DRAM_DEV_SEL(n) ((n > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
290 DRAM_TYPE_DDR1 = 1,
488 static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value, in emc_ccfifo_writel() argument
491 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()
492 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel()
[all …]

1234