| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | tegra124-nyan-blaze-emc.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 emc-timings-1 {
5 nvidia,ram-code = <1>;
7 timing-12750000 {
8 clock-frequency = <12750000>;
9 nvidia,parent-clock-frequency = <408000000>;
11 clock-names = "emc-parent";
13 timing-20400000 {
14 clock-frequency = <20400000>;
15 nvidia,parent-clock-frequency = <408000000>;
[all …]
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| D | tegra124-nyan-big-emc.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 emc-timings-1 {
5 nvidia,ram-code = <1>;
7 timing-12750000 {
8 clock-frequency = <12750000>;
9 nvidia,parent-clock-frequency = <408000000>;
11 clock-names = "emc-parent";
13 timing-20400000 {
14 clock-frequency = <20400000>;
15 nvidia,parent-clock-frequency = <408000000>;
[all …]
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| D | tegra124-jetson-tk1-emc.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 emc-timings-3 {
5 nvidia,ram-code = <3>;
7 timing-12750000 {
8 clock-frequency = <12750000>;
9 nvidia,parent-clock-frequency = <408000000>;
11 clock-names = "emc-parent";
13 timing-20400000 {
14 clock-frequency = <20400000>;
15 nvidia,parent-clock-frequency = <408000000>;
[all …]
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| D | tegra124-apalis-emc.dtsi | 4 * This file is dual-licensed: you can use it either under the terms
44 emc-timings-1 {
45 nvidia,ram-code = <1>;
47 timing-12750000 {
48 clock-frequency = <12750000>;
49 nvidia,parent-clock-frequency = <408000000>;
51 clock-names = "emc-parent";
53 timing-20400000 {
54 clock-frequency = <20400000>;
55 nvidia,parent-clock-frequency = <408000000>;
[all …]
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| D | lpc4357-ea4357-devkit.dts | 9 * Released under the terms of 3-clause BSD License
13 /dts-v1/;
18 #include "dt-bindings/input/input.h"
19 #include "dt-bindings/gpio/gpio.h"
23 compatible = "ea,lpc4357-developers-kit", "nxp,lpc4357", "nxp,lpc4350";
33 stdout-path = &uart0;
42 compatible = "regulator-fixed";
43 regulator-name = "3v3-supply";
44 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>;
[all …]
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| D | lpc4350-hitex-eval.dts | 9 * Released under the terms of 3-clause BSD License
13 /dts-v1/;
18 #include "dt-bindings/input/input.h"
19 #include "dt-bindings/gpio/gpio.h"
23 compatible = "hitex,lpc4350-eval-board", "nxp,lpc4350";
33 stdout-path = &uart0;
42 compatible = "gpio-keys-polled";
43 #address-cells = <1>;
44 #size-cells = <0>;
45 poll-interval = <100>;
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | tegra124-nyan-blaze-emc.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 emc-timings-1 {
5 nvidia,ram-code = <1>;
7 timing-12750000 {
8 clock-frequency = <12750000>;
9 nvidia,parent-clock-frequency = <408000000>;
11 clock-names = "emc-parent";
13 timing-20400000 {
14 clock-frequency = <20400000>;
15 nvidia,parent-clock-frequency = <408000000>;
[all …]
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| D | tegra124-apalis-emc.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Copyright 2016-2019 Toradex AG
9 emc-timings-1 {
10 nvidia,ram-code = <1>;
12 timing-12750000 {
13 clock-frequency = <12750000>;
14 nvidia,parent-clock-frequency = <408000000>;
16 clock-names = "emc-parent";
18 timing-20400000 {
19 clock-frequency = <20400000>;
[all …]
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| D | tegra124-jetson-tk1-emc.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 emc-timings-3 {
5 nvidia,ram-code = <3>;
7 timing-12750000 {
8 clock-frequency = <12750000>;
9 nvidia,parent-clock-frequency = <408000000>;
11 clock-names = "emc-parent";
13 timing-20400000 {
14 clock-frequency = <20400000>;
15 nvidia,parent-clock-frequency = <408000000>;
[all …]
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| D | tegra124-nyan-big-emc.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 nvidia,long-ram-code;
8 emc-timings-1 {
9 nvidia,ram-code = <1>;
11 timing-12750000 {
12 clock-frequency = <12750000>;
13 nvidia,parent-clock-frequency = <408000000>;
15 clock-names = "emc-parent";
17 timing-20400000 {
18 clock-frequency = <20400000>;
[all …]
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| D | tegra20-acer-a500-picasso.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra20-cpu-opp.dtsi"
10 #include "tegra20-cpu-opp-microvolt.dtsi"
31 * pre-existing /chosen node to be available to insert the
40 reserved-memory {
41 #address-cells = <1>;
[all …]
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| D | lpc4357-ea4357-devkit.dts | 9 * Released under the terms of 3-clause BSD License
13 /dts-v1/;
18 #include "dt-bindings/input/input.h"
19 #include "dt-bindings/gpio/gpio.h"
23 compatible = "ea,lpc4357-developers-kit", "nxp,lpc4357", "nxp,lpc4350";
33 stdout-path = &uart0;
42 compatible = "regulator-fixed";
43 regulator-name = "3v3-supply";
44 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>;
[all …]
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| D | lpc4350-hitex-eval.dts | 9 * Released under the terms of 3-clause BSD License
13 /dts-v1/;
18 #include "dt-bindings/input/input.h"
19 #include "dt-bindings/gpio/gpio.h"
23 compatible = "hitex,lpc4350-eval-board", "nxp,lpc4350";
33 stdout-path = &uart0;
42 compatible = "gpio-keys-polled";
43 poll-interval = <100>;
97 compatible = "gpio-leds";
102 linux,default-trigger = "heartbeat";
[all …]
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| D | lpc4357-myd-lpc4357.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * MYIR Tech MYD-LPC4357 Development Board with 800x480 7" TFT panel
5 * Copyright (C) 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
8 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
17 compatible = "myir,myd-lpc4357", "nxp,lpc4357";
20 stdout-path = "serial3:115200n8";
29 compatible = "gpio-leds";
30 pinctrl-names = "default";
31 pinctrl-0 = <&led_pins>;
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra124-emc.txt | 1 NVIDIA Tegra124 SoC EMC (external memory controller)
5 - compatible : Should be "nvidia,tegra124-emc".
6 - reg : physical base address and length of the controller's registers.
7 - nvidia,memory-controller : phandle of the MC driver.
9 The node should contain a "emc-timings" subnode for each supported RAM type
13 Required properties for "emc-timings" nodes :
14 - nvidia,ram-code : Should contain the value of RAM_CODE this timing set is
17 Each "emc-timings" node should contain a "timing" subnode for every supported
18 EMC clock rate. The "timing" subnodes should have the clock rate in Hz as
22 - clock-frequency : Should contain the memory clock rate in Hz.
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra124-emc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The EMC interfaces with the off-chip SDRAM to service the request stream
19 const: nvidia,tegra124-emc
26 - description: external memory clock
28 clock-names:
[all …]
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| D | nvidia,tegra30-emc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The EMC interfaces with the off-chip SDRAM to service the request stream
16 sent from Memory Controller. The EMC also has various performance-affecting
18 settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
[all …]
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| /kernel/linux/linux-4.19/drivers/memory/tegra/ |
| D | tegra124-emc.c | 18 #include <linux/clk-provider.h>
29 #include <soc/tegra/emc.h>
38 #define EMC_INTSTATUS_CLKCHANGE_COMPLETE BIT(4)
153 #define EMC_ZQ_CAL_LONG BIT(4)
204 #define EMC_SEL_DPD_CTRL_RESET_SEL_DPD BIT(4)
488 static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value, in emc_ccfifo_writel() argument
491 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()
492 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel()
495 static void emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument
500 writel(1, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
[all …]
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| /kernel/linux/linux-5.10/drivers/memory/tegra/ |
| D | tegra124-emc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
21 #include <soc/tegra/emc.h>
30 #define EMC_INTSTATUS_CLKCHANGE_COMPLETE BIT(4)
145 #define EMC_ZQ_CAL_LONG BIT(4)
196 #define EMC_SEL_DPD_CTRL_RESET_SEL_DPD BIT(4)
488 static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value, in emc_ccfifo_writel() argument
491 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()
492 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel()
495 static void emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument
[all …]
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| D | tegra30-emc.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
6 * Copyright (C) 2011-2014 NVIDIA Corporation
9 * Copyright (C) 2019 GRATE-DRIVER project
154 #define EMC_ZQ_CAL_LONG BIT(4)
175 #define EMC_XM2QUSEPADCTRL_IVREF_ENABLE BIT(4)
205 #define EMC_CLKCHANGE_COMPLETE_INT BIT(4)
225 [4] = EMC_R2W,
357 static int emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument
362 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
[all …]
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| D | tegra20-emc.c | 1 // SPDX-License-Identifier: GPL-2.0
83 #define EMC_CLKCHANGE_COMPLETE_INT BIT(4)
163 struct tegra_emc *emc = data; in tegra_emc_isr() local
167 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
173 dev_err_ratelimited(emc->dev, in tegra_emc_isr()
177 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
182 static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc, in tegra_emc_find_timing() argument
188 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_find_timing()
189 if (emc->timings[i].rate >= rate) { in tegra_emc_find_timing()
190 timing = &emc->timings[i]; in tegra_emc_find_timing()
[all …]
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| D | tegra210-emc-cc-r21021.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
14 #include "tegra210-emc.h"
15 #include "tegra210-mc.h"
24 #define PRELOCK_STEPS (1 << 4)
36 #define emc_dbg(emc, flags, ...) dev_dbg(emc->dev, __VA_ARGS__) argument
53 * PTFV defines - basically just indexes into the per table PTFV array.
59 #define PTFV_DQSOSC_MOVAVG_C1D0U0_INDEX 4
78 ({ next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] = \
79 next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] / \
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-lpc32xx/ |
| D | suspend.S | 2 * arch/arm/mach-lpc32xx/suspend.S
41 stmfd r0!, {r3 - r7, sp, lr}
46 ldr EMCBASE_REG, [WORK1_REG, #4]
65 @ Setup self-refresh with support for manual exit of
66 @ self-refresh mode
72 @ Wait for self-refresh acknowledge, clocks to the DRAM device
73 @ will automatically stop on start of self-refresh
78 bne 3b @ Branch until self-refresh mode starts
80 @ Enter direct-run mode from run mode
84 @ Safe disable of DRAM clock in EMC block, prevents DDR sync
[all …]
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| /kernel/linux/linux-4.19/arch/arm/mach-lpc32xx/ |
| D | suspend.S | 2 * arch/arm/mach-lpc32xx/suspend.S
42 stmfd r0!, {r3 - r7, sp, lr}
47 ldr EMCBASE_REG, [WORK1_REG, #4]
66 @ Setup self-refresh with support for manual exit of
67 @ self-refresh mode
73 @ Wait for self-refresh acknowledge, clocks to the DRAM device
74 @ will automatically stop on start of self-refresh
79 bne 3b @ Branch until self-refresh mode starts
81 @ Enter direct-run mode from run mode
85 @ Safe disable of DRAM clock in EMC block, prevents DDR sync
[all …]
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| /kernel/linux/linux-5.10/arch/s390/include/uapi/asm/ |
| D | dasd.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
6 * EMC Symmetrix ioctl Copyright EMC Corporation, 2008
7 * Author.........: Nigel Hislop <hislop_nigel@emc.com>
11 * to userspace by the DASDAPIVER-ioctl
40 char type[4]; /* from discipline.name, 'none' for unknown */
110 char type[4]; /* from discipline.name, 'none' for unknown */
121 * Read Subsystem Data - Performance Statistics
126 unsigned char data_format:4;
190 * 4/12: invalidate track
194 #define DASD_FMT_INT_INVAL 4 /* invalidate tracks */
[all …]
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