| /kernel/linux/linux-5.10/arch/arm64/boot/dts/cavium/ |
| D | thunder-88xx.dtsi | 2 * Cavium Thunder DTS file - Thunder SoC description
6 * This file is dual-licensed: you can use it either under the terms
24 * MA 02110-1301 USA
51 compatible = "cavium,thunder-88xx";
52 interrupt-parent = <&gic0>;
53 #address-cells = <2>;
54 #size-cells = <2>;
57 compatible = "arm,psci-0.2";
58 method = "smc";
62 #address-cells = <2>;
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| /kernel/linux/linux-4.19/arch/arm64/boot/dts/cavium/ |
| D | thunder-88xx.dtsi | 2 * Cavium Thunder DTS file - Thunder SoC description
6 * This file is dual-licensed: you can use it either under the terms
24 * MA 02110-1301 USA
51 compatible = "cavium,thunder-88xx";
52 interrupt-parent = <&gic0>;
53 #address-cells = <2>;
54 #size-cells = <2>;
57 compatible = "arm,psci-0.2";
58 method = "smc";
62 #address-cells = <2>;
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| /kernel/linux/linux-4.19/Documentation/acpi/ |
| D | method-tracing.txt | 9 This document describes the functions and the interfaces of the method
14 ACPICA provides method tracing capability. And two functions are
20 ACPI_DEBUG_PRINT() macro can be reduced at 2 levels - per-component
22 /sys/module/acpi/parameters/debug_layer) and per-type level (known as
25 But when the particular layer/level is applied to the control method
28 to only enable the particular debug layer/level (normally more detailed)
29 logs when the control method evaluation is started, and disable the
30 detailed logging when the control method evaluation is stopped.
39 # echo "enable" > trace_state
41 control method is being evaluated:
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| /kernel/linux/linux-5.10/Documentation/firmware-guide/acpi/ |
| D | method-tracing.rst | 1 .. SPDX-License-Identifier: GPL-2.0
15 method tracing facility.
20 ACPICA provides method tracing capability. And two functions are
24 -----------
28 ACPI_DEBUG_PRINT() macro can be reduced at 2 levels - per-component
30 /sys/module/acpi/parameters/debug_layer) and per-type level (known as
33 But when the particular layer/level is applied to the control method
36 to only enable the particular debug layer/level (normally more detailed)
37 logs when the control method evaluation is started, and disable the
38 detailed logging when the control method evaluation is stopped.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | cpus.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/marvell/ |
| D | armada-ap810-ap0-octa-core.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap810-ap0.dtsi"
12 #address-cells = <1>;
13 #size-cells = <0>;
14 compatible = "marvell,armada-ap810-octa";
18 compatible = "arm,cortex-a72";
20 enable-method = "psci";
24 compatible = "arm,cortex-a72";
26 enable-method = "psci";
30 compatible = "arm,cortex-a72";
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| /kernel/linux/linux-4.19/arch/arm64/boot/dts/marvell/ |
| D | armada-ap810-ap0-octa-core.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap810-ap0.dtsi"
12 #address-cells = <1>;
13 #size-cells = <0>;
14 compatible = "marvell,armada-ap810-octa";
18 compatible = "arm,cortex-a72", "arm,armv8";
20 enable-method = "psci";
24 compatible = "arm,cortex-a72", "arm,armv8";
26 enable-method = "psci";
30 compatible = "arm,cortex-a72", "arm,armv8";
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| /kernel/linux/linux-5.10/arch/arm/kernel/ |
| D | cpuidle.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
19 * arm_cpuidle_simple_enter() - a wrapper to cpu_do_idle()
38 * arm_cpuidle_suspend() - function to enter low power idle states
54 * arm_cpuidle_get_ops() - find a registered cpuidle_ops by name
55 * @method: the method name
58 * method name.
62 static const struct cpuidle_ops *__init arm_cpuidle_get_ops(const char *method) in arm_cpuidle_get_ops() argument
66 for (; m->method; m++) in arm_cpuidle_get_ops()
67 if (!strcmp(m->method, method)) in arm_cpuidle_get_ops()
68 return m->ops; in arm_cpuidle_get_ops()
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| /kernel/linux/linux-4.19/arch/arm/kernel/ |
| D | cpuidle.c | 8 * http://www.opensource.org/licenses/gpl-license.html
25 * arm_cpuidle_simple_enter() - a wrapper to cpu_do_idle()
44 * arm_cpuidle_suspend() - function to enter low power idle states
60 * arm_cpuidle_get_ops() - find a registered cpuidle_ops by name
61 * @method: the method name
64 * method name.
68 static const struct cpuidle_ops *__init arm_cpuidle_get_ops(const char *method) in arm_cpuidle_get_ops() argument
72 for (; m->method; m++) in arm_cpuidle_get_ops()
73 if (!strcmp(m->method, method)) in arm_cpuidle_get_ops()
74 return m->ops; in arm_cpuidle_get_ops()
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/ |
| D | cpus.txt | 13 with updates for 32-bit and 64-bit ARM systems provided in this document.
22 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
33 - cpus node
41 - #address-cells
49 value must be 1, to enable a simple enumeration
52 # On 32-bit ARM 11 MPcore, ARM v7 or later systems
55 # On ARM v8 64-bit systems value should be set to 2,
58 in the system, #address-cells can be set to 1, since
61 - #size-cells
66 - cpu node
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/hisilicon/ |
| D | hip05.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip05-d02";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
18 method = "smc";
22 #address-cells = <1>;
23 #size-cells = <0>;
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| /kernel/linux/linux-4.19/arch/arm64/boot/dts/hisilicon/ |
| D | hip05.dtsi | 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 compatible = "hisilicon,hip05-d02";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 compatible = "arm,psci-0.2";
22 method = "smc";
26 #address-cells = <1>;
27 #size-cells = <0>;
29 cpu-map {
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|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/bcm/ |
| D | brcm,bcm11351-cpu-method.txt | 1 Broadcom Kona Family CPU Enable Method
2 --------------------------------------
3 This binding defines the enable method used for starting secondary
7 The enable method is specified by defining the following required
9 - enable-method = "brcm,bcm11351-cpu-method";
10 - secondary-boot-reg = <...>;
12 The secondary-boot-reg property is a u32 value that specifies the
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a9";
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|
| /kernel/linux/linux-4.19/Documentation/PCI/ |
| D | pci-iov-howto.txt | 6 -- sysfs-based SRIOV enable-/disable-ment
11 1.1 What is SR-IOV
13 Single Root I/O Virtualization (SR-IOV) is a PCI Express Extended
28 2.1 How can I enable SR-IOV capability
30 Multiple methods are available for SR-IOV enablement.
31 In the first method, the device driver (PF driver) will control the
32 enabling and disabling of the capability via API provided by SR-IOV core.
33 If the hardware has SR-IOV capability, loading its PF driver would
34 enable it and all VFs associated with the PF. Some PF drivers require
35 a module parameter to be set to determine the number of VFs to enable.
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/mediatek/ |
| D | mt6755.dtsi | 14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
21 #size-cells = <2>;
24 compatible = "arm,psci-0.2";
25 method = "smc";
29 #address-cells = <1>;
30 #size-cells = <0>;
34 compatible = "arm,cortex-a53";
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|
| D | mt6795.dtsi | 14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
21 #size-cells = <2>;
24 compatible = "arm,psci-0.2";
25 method = "smc";
29 #address-cells = <1>;
30 #size-cells = <0>;
34 compatible = "arm,cortex-a53";
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| /kernel/linux/linux-4.19/arch/arm64/boot/dts/mediatek/ |
| D | mt6755.dtsi | 14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
21 #size-cells = <2>;
24 compatible = "arm,psci-0.2";
25 method = "smc";
29 #address-cells = <1>;
30 #size-cells = <0>;
34 compatible = "arm,cortex-a53";
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|
| D | mt6795.dtsi | 14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
21 #size-cells = <2>;
24 compatible = "arm,psci-0.2";
25 method = "smc";
29 #address-cells = <1>;
30 #size-cells = <0>;
34 compatible = "arm,cortex-a53";
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|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/ |
| D | numa.txt | 6 1 - Introduction
18 2 - numa-node-id
23 a node id is a 32-bit integer.
26 numa-node-id property which contains the node id of the device.
30 numa-node-id = <0>;
33 numa-node-id = <1>;
36 3 - distance-map
39 The optional device tree node distance-map describes the relative
42 - compatible : Should at least contain "numa-distance-map-v1".
44 - distance-matrix
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/ |
| D | numa.txt | 6 1 - Introduction
18 2 - numa-node-id
23 a node id is a 32-bit integer.
26 numa-node-id property which contains the node id of the device.
30 numa-node-id = <0>;
33 numa-node-id = <1>;
36 3 - distance-map
39 The optional device tree node distance-map describes the relative
42 - compatible : Should at least contain "numa-distance-map-v1".
44 - distance-matrix
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|
| /kernel/linux/linux-5.10/arch/arm64/kernel/ |
| D | cpu_ops.c | 1 // SPDX-License-Identifier: GPL-2.0-only
46 if (!strcmp(name, (*ops)->name)) in cpu_get_ops()
68 enable_method = of_get_property(dn, "enable-method", NULL); in cpu_read_enable_method()
71 * The boot CPU may not have an enable method (e.g. in cpu_read_enable_method()
72 * when spin-table is used for secondaries). in cpu_read_enable_method()
76 pr_err("%pOF: missing enable-method property\n", in cpu_read_enable_method()
85 * checking the enable method since for some in cpu_read_enable_method()
90 pr_err("Unsupported ACPI enable-method\n"); in cpu_read_enable_method()
97 * Read a cpu's enable method and record it in cpu_ops.
104 return -ENODEV; in init_cpu_ops()
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| /kernel/linux/linux-4.19/arch/arm64/boot/dts/arm/ |
| D | foundation-v8-psci.dtsi | 9 compatible = "arm,psci-1.0";
10 method = "smc";
15 enable-method = "psci";
19 enable-method = "psci";
23 enable-method = "psci";
27 enable-method = "psci";
|
| /kernel/linux/linux-5.10/arch/arm64/boot/dts/arm/ |
| D | foundation-v8-psci.dtsi | 9 compatible = "arm,psci-1.0";
10 method = "smc";
15 enable-method = "psci";
19 enable-method = "psci";
23 enable-method = "psci";
27 enable-method = "psci";
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/cpu-enable-method/ |
| D | marvell,berlin-smp | 2 Secondary CPU enable-method "marvell,berlin-smp" binding
5 This document describes the "marvell,berlin-smp" method for enabling secondary
6 CPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should
9 Enable method name: "marvell,berlin-smp"
11 Compatible CPUs: "marvell,pj4b" and "arm,cortex-a9"
15 This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
16 "marvell,berlin-cpu-ctrl"[1].
21 #address-cells = <1>;
22 #size-cells = <0>;
23 enable-method = "marvell,berlin-smp";
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|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/cpu-enable-method/ |
| D | marvell,berlin-smp | 2 Secondary CPU enable-method "marvell,berlin-smp" binding
5 This document describes the "marvell,berlin-smp" method for enabling secondary
6 CPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should
9 Enable method name: "marvell,berlin-smp"
11 Compatible CPUs: "marvell,pj4b" and "arm,cortex-a9"
15 This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
16 "marvell,berlin-cpu-ctrl"[1].
21 #address-cells = <1>;
22 #size-cells = <0>;
23 enable-method = "marvell,berlin-smp";
[all …]
|