| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/net/ |
| D | altera_tse.txt | 1 * Altera Triple-Speed Ethernet MAC driver (TSE)
4 - compatible: Should be "altr,tse-1.0" for legacy SGDMA based TSE, and should
5 be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE.
8 - reg: Address and length of the register set for the device. It contains
9 the information of registers in the same order as described by reg-names
10 - reg-names: Should contain the reg names
18 - interrupts: Should contain the TSE interrupts and it's mode.
19 - interrupt-names: Should contain the interrupt names
22 - rx-fifo-depth: MAC receive FIFO buffer depth in bytes
23 - tx-fifo-depth: MAC transmit FIFO buffer depth in bytes
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | altera_tse.txt | 1 * Altera Triple-Speed Ethernet MAC driver (TSE)
4 - compatible: Should be "altr,tse-1.0" for legacy SGDMA based TSE, and should
5 be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE.
8 - reg: Address and length of the register set for the device. It contains
9 the information of registers in the same order as described by reg-names
10 - reg-names: Should contain the reg names
18 - interrupts: Should contain the TSE interrupts and it's mode.
19 - interrupt-names: Should contain the interrupt names
22 - rx-fifo-depth: MAC receive FIFO buffer depth in bytes
23 - tx-fifo-depth: MAC transmit FIFO buffer depth in bytes
[all …]
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| D | adi,adin.yaml | 1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Ardelean <alexandru.ardelean@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
29 internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
33 adi,fifo-depth-bits:
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/amlogic/ |
| D | meson-sm1.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12-common.dtsi"
8 #include <dt-bindings/clock/axg-audio-clkc.h>
9 #include <dt-bindings/power/meson-sm1-power.h>
10 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
11 #include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h>
16 tdmif_a: audio-controller-0 {
17 compatible = "amlogic,axg-tdm-iface";
18 #sound-dai-cells = <0>;
19 sound-name-prefix = "TDM_A";
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/ |
| D | spi-sifive.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
15 - $ref: "spi-controller.yaml#"
20 - const: sifive,fu540-c000-spi
21 - const: sifive,spi0
[all …]
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| /kernel/liteos_m/targets/riscv_nuclei_gd32vf103_soc_gcc/SoC/gd32vf103/Common/Include/Usb/ |
| D | drv_usb_regs.h | 5 \version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS
43 #define USBFS_MAX_TX_FIFOS 15 /*!< FIFO number */
48 #define USBFS_MAX_FIFO_WORDLEN 320U /*!< USBFS max fifo size in words */
53 #define USBHS_MAX_FIFO_WORDLEN 1280U /*!< USBHS max fifo size in words */
55 #define USB_DATA_FIFO_OFFSET 0x1000U /*!< USB data fifo offset */
56 #define USB_DATA_FIFO_SIZE 0x1000U /*!< USB data fifo size */
73 USB_REG_OFFSET_CH_INOUT = 0x0500U, /*!< Host channel-x control registers */
88 …__IO uint32_t GRFLEN; /*!< USB global receive FIFO length register …
89 …LEN_HNPTFLEN; /*!< USB device IN endpoint 0/host non-periodic transmit FIFO length re…
90 …__IO uint32_t HNPTFQSTAT; /*!< USB host non-periodic FIFO/queue status regis…
[all …]
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| /kernel/linux/linux-4.19/drivers/net/ethernet/sgi/ |
| D | meth.h | 3 * snull.h -- definitions for the network module
20 #define TX_RING_ENTRIES 64 /* 64-512?*/
27 #define METH_RX_HEAD 34 /* status + 3 quad garbage-fill + 2 byte zero-pad */
48 * It consists of header, 0-3 concatination
59 u64 data_len:16; /*Length of valid data in bytes-1*/
64 u64 len:16; /*length of buffer data - 1*/
107 u64 pad[3]; /* For whatever reason, there needs to be 4 double-word offset */
109 char buf[METH_RX_BUFF_SIZE-sizeof(rx_status_vector)-3*sizeof(u64)-sizeof(u16)];/* data */
115 /* Bits in METH_MAC */
126 /* Bits 5 and 6 are used to determine the Destination address filter mode */
[all …]
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| /kernel/linux/linux-5.10/drivers/net/ethernet/sgi/ |
| D | meth.h | 4 #define TX_RING_ENTRIES 64 /* 64-512?*/
11 #define METH_RX_HEAD 34 /* status + 3 quad garbage-fill + 2 byte zero-pad */
32 * It consists of header, 0-3 concatination
43 u64 data_len:16; /*Length of valid data in bytes-1*/
48 u64 len:16; /*length of buffer data - 1*/
91 u64 pad[3]; /* For whatever reason, there needs to be 4 double-word offset */
93 char buf[METH_RX_BUFF_SIZE-sizeof(rx_status_vector)-3*sizeof(u64)-sizeof(u16)];/* data */
99 /* Bits in METH_MAC */
110 /* Bits 5 and 6 are used to determine the Destination address filter mode */
122 … /* Bits 8 through 14 are used to determine Inter-Packet Gap between "Back to Back" packets */
[all …]
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| /kernel/linux/linux-4.19/include/linux/ |
| D | qcom-geni-se.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
29 * struct geni_se - GENI Serial Engine
242 * geni_se_read_proto() - Read the protocol configured for a serial engine
251 val = readl_relaxed(se->base + GENI_FW_REVISION_RO); in geni_se_read_proto()
257 * geni_se_setup_m_cmd() - Setup the primary sequencer
270 writel_relaxed(m_cmd, se->base + SE_GENI_M_CMD0); in geni_se_setup_m_cmd()
274 * geni_se_setup_s_cmd() - Setup the secondary sequencer
286 s_cmd = readl_relaxed(se->base + SE_GENI_S_CMD0); in geni_se_setup_s_cmd()
290 writel_relaxed(s_cmd, se->base + SE_GENI_S_CMD0); in geni_se_setup_s_cmd()
[all …]
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| /kernel/linux/linux-5.10/include/linux/ |
| D | qcom-geni-se.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
42 * struct geni_se - GENI Serial Engine
274 * geni_se_read_proto() - Read the protocol configured for a serial engine
283 val = readl_relaxed(se->base + GENI_FW_REVISION_RO); in geni_se_read_proto()
289 * geni_se_setup_m_cmd() - Setup the primary sequencer
302 writel(m_cmd, se->base + SE_GENI_M_CMD0); in geni_se_setup_m_cmd()
306 * geni_se_setup_s_cmd() - Setup the secondary sequencer
318 s_cmd = readl_relaxed(se->base + SE_GENI_S_CMD0); in geni_se_setup_s_cmd()
322 writel(s_cmd, se->base + SE_GENI_S_CMD0); in geni_se_setup_s_cmd()
[all …]
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| /kernel/linux/linux-5.10/drivers/net/phy/ |
| D | dp83867.c | 1 // SPDX-License-Identifier: GPL-2.0
18 #include <dt-bindings/net/ti-dp83867.h>
59 /* MICR Interrupt bits */
73 /* RGMIICTL bits */
77 /* SGMIICTL bits */
80 /* RXFCFG bits*/
87 /* STRAP_STS1 bits */
90 /* STRAP_STS2 bits */
98 /* PHY CTRL bits */
107 /* RGMIIDCTL bits */
[all …]
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| /kernel/linux/linux-5.10/drivers/spi/ |
| D | spi-sifive.c | 1 // SPDX-License-Identifier: GPL-2.0
34 #define SIFIVE_SPI_REG_TXDATA 0x48 /* Tx FIFO data */
35 #define SIFIVE_SPI_REG_RXDATA 0x4c /* Rx FIFO data */
36 #define SIFIVE_SPI_REG_TXMARK 0x50 /* Tx FIFO watermark */
37 #define SIFIVE_SPI_REG_RXMARK 0x54 /* Rx FIFO watermark */
43 /* sckdiv bits */
46 /* sckmode bits */
52 /* csmode bits */
57 /* delay0 bits */
63 /* delay1 bits */
[all …]
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| /kernel/linux/linux-4.19/sound/soc/meson/ |
| D | axg-toddr.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
14 #include <sound/soc-dai.h>
16 #include "axg-fifo.h"
38 struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai); in axg_toddr_dai_hw_params() local
50 type = 0; /* 8 samples of 8 bits */ in axg_toddr_dai_hw_params()
53 type = 2; /* 4 samples of 16 bits - right justified */ in axg_toddr_dai_hw_params()
56 type = 4; /* 2 samples of 32 bits - right justified */ in axg_toddr_dai_hw_params()
59 return -EINVAL; in axg_toddr_dai_hw_params()
64 regmap_update_bits(fifo->map, FIFO_CTRL0, in axg_toddr_dai_hw_params()
70 CTRL0_TODDR_LSB_POS(msb - (width - 1))); in axg_toddr_dai_hw_params()
[all …]
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| /kernel/linux/linux-5.10/include/media/drv-intf/ |
| D | exynos-fimc.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2010 - 2013 Samsung Electronics Co., Ltd.
12 #include <media/media-entity.h>
13 #include <media/v4l2-dev.h>
14 #include <media/v4l2-mediabus.h>
37 /* Camera MIPI-CSI2 serial bus */
39 /* FIFO link from LCD controller (WriteBack A) */
41 /* FIFO link from LCD controller (WriteBack B) */
43 /* FIFO link from FIMC-IS */
62 * struct fimc_source_info - video source description required for the host
[all …]
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| /kernel/linux/linux-4.19/include/media/drv-intf/ |
| D | exynos-fimc.h | 4 * Copyright (C) 2010 - 2013 Samsung Electronics Co., Ltd.
15 #include <media/media-entity.h>
16 #include <media/v4l2-dev.h>
17 #include <media/v4l2-mediabus.h>
40 /* Camera MIPI-CSI2 serial bus */
42 /* FIFO link from LCD controller (WriteBack A) */
44 /* FIFO link from LCD controller (WriteBack B) */
46 /* FIFO link from FIMC-IS */
65 * struct fimc_source_info - video source description required for the host
69 * @sensor_bus_type: image sensor bus type, MIPI, ITU-R BT.601 etc.
[all …]
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| /kernel/linux/linux-5.10/arch/nios2/boot/dts/ |
| D | 10m50_devboard.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
10 compatible = "altr,niosii-max10";
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "altr,nios2-1.1";
22 interrupt-controller;
23 #interrupt-cells = <1>;
[all …]
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| D | 3c120_devboard.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "altr,nios2-1.0";
24 interrupt-controller;
25 #interrupt-cells = <1>;
26 clock-frequency = <125000000>;
[all …]
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| /kernel/linux/linux-4.19/arch/nios2/boot/dts/ |
| D | 10m50_devboard.dts | 17 /dts-v1/;
21 compatible = "altr,niosii-max10";
22 #address-cells = <1>;
23 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
31 compatible = "altr,nios2-1.1";
33 interrupt-controller;
34 #interrupt-cells = <1>;
35 altr,exception-addr = <0xc8000120>;
[all …]
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| D | 3c120_devboard.dts | 20 /dts-v1/;
25 #address-cells = <1>;
26 #size-cells = <1>;
29 #address-cells = <1>;
30 #size-cells = <0>;
34 compatible = "altr,nios2-1.0";
36 interrupt-controller;
37 #interrupt-cells = <1>;
38 clock-frequency = <125000000>;
39 dcache-line-size = <32>;
[all …]
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| /kernel/linux/linux-5.10/drivers/staging/axis-fifo/ |
| D | axis-fifo.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx AXIS FIFO: interface to the Xilinx AXI-Stream FIFO IP core
12 /* ----------------------------
14 * ----------------------------
38 /* ----------------------------
40 * ----------------------------
48 /* ----------------------------
50 * ----------------------------
69 /* ----------------------------
71 * ----------------------------
[all …]
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| /kernel/linux/linux-4.19/drivers/i2c/busses/ |
| D | i2c-cadence.c | 4 * Copyright (C) 2009 - 2014 Xilinx, Inc.
41 /* 1 = Auto init FIFO to zeroes */
54 * Normal addressing mode uses [6:0] bits. Extended addressing mode uses [9:0]
55 * bits. A write access to this register always initiates a transfer if the I2C
104 /* FIFO depth at which the DATA interrupt occurs */
105 #define CDNS_I2C_DATA_INTR_DEPTH (CDNS_I2C_FIFO_DEPTH - 2)
107 /* Transfer size in multiples of data interrupt depth */
108 #define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_MAX_TRANSFER_SIZE - 3)
110 #define DRIVER_NAME "cdns-i2c"
122 #define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset)
[all …]
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| /kernel/linux/linux-5.10/sound/soc/fsl/ |
| D | fsl_dma.c | 1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
16 #include <linux/dma-mapping.h>
40 * that is 8, 16, or 32 bits.
72 /** fsl_dma_private: p-substream DMA data
74 * Each substream has a 1-to-1 association with a DMA channel.
76 * The link[] array is first because it needs to be aligned on a 32-byte
120 * Since each link descriptor has a 32-bit byte count field, we set
121 * period_bytes_max to the largest 32-bit number. We also have no maximum
137 .period_bytes_max = (u32) -1,
[all …]
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| /kernel/linux/linux-4.19/sound/soc/fsl/ |
| D | fsl_dma.c | 6 * Copyright 2007-2010 Freescale Semiconductor, Inc.
20 #include <linux/dma-mapping.h>
44 * that is 8, 16, or 32 bits.
76 /** fsl_dma_private: p-substream DMA data
78 * Each substream has a 1-to-1 association with a DMA channel.
80 * The link[] array is first because it needs to be aligned on a 32-byte
124 * Since each link descriptor has a 32-bit byte count field, we set
125 * period_bytes_max to the largest 32-bit number. We also have no maximum
141 .period_bytes_max = (u32) -1,
143 .periods_max = (unsigned int) -1,
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/zte/ |
| D | zx296718.dtsi | 5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/input/input.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/gpio/gpio.h>
47 #include <dt-bindings/clock/zx296718-clock.h>
51 #address-cells = <1>;
52 #size-cells = <1>;
53 interrupt-parent = <&gic>;
67 #address-cells = <2>;
68 #size-cells = <0>;
[all …]
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| /kernel/linux/linux-4.19/arch/arm64/boot/dts/zte/ |
| D | zx296718.dtsi | 5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/input/input.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/gpio/gpio.h>
47 #include <dt-bindings/clock/zx296718-clock.h>
51 #address-cells = <1>;
52 #size-cells = <1>;
53 interrupt-parent = <&gic>;
67 #address-cells = <2>;
68 #size-cells = <0>;
[all …]
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