Home
last modified time | relevance | path

Searched +full:fifo +full:- +full:watermark +full:- +full:aligned (Results 1 – 25 of 64) sorted by relevance

123

/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/
Dsynopsys-dw-mshc-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: "mmc-controller.yaml#"
13 - Ulf Hansson <ulf.hansson@linaro.org>
20 reset-names:
23 clock-frequency:
29 fifo-depth:
31 The maximum size of the tx/rx fifo's. If this property is not
[all …]
Dzx-dw-mshc.txt7 by synopsys-dw-mshc.txt and the properties used by the ZTE specific
13 - "zte,zx296718-dw-mshc": for ZX SoCs
18 compatible = "zte,zx296718-dw-mshc";
21 fifo-depth = <32>;
22 data-addr = <0x200>;
23 fifo-watermark-aligned;
24 bus-width = <4>;
25 clock-frequency = <50000000>;
27 clock-names = "biu", "ciu";
28 max-frequency = <50000000>;
[all …]
Dsynopsys-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: "synopsys-dw-mshc-common.yaml#"
13 - Ulf Hansson <ulf.hansson@linaro.org>
18 const: snps,dw-mshc
33 clock-names:
35 - const: biu
36 - const: ciu
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/mmc/
Dsynopsys-dw-mshc.txt11 - snps,dw-mshc: for controllers compliant with synopsys dw-mshc.
12 * #address-cells: should be 1.
13 * #size-cells: should be 0.
16 child-nodes with each child-node representing a supported slot. There should
23 property is 0 to (num-slots -1), where num-slots is the value
24 specified by the num-slots property.
26 * bus-width: as documented in mmc core bindings.
28 * wp-gpios: specifies the write protect gpio line. The format of the
30 for write-protect, this property is optional.
32 * disable-wp: If the wp-gpios property isn't present then (by default)
[all …]
Dzx-dw-mshc.txt7 by synopsys-dw-mshc.txt and the properties used by the ZTE specific
13 - "zte,zx296718-dw-mshc": for ZX SoCs
18 compatible = "zte,zx296718-dw-mshc";
21 fifo-depth = <32>;
22 data-addr = <0x200>;
23 fifo-watermark-aligned;
24 bus-width = <4>;
25 clock-frequency = <50000000>;
27 clock-names = "biu", "ciu";
28 max-frequency = <50000000>;
[all …]
/kernel/linux/linux-5.10/drivers/iio/imu/inv_icm42600/
Dinv_icm42600_buffer.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
19 * struct inv_icm42600_fifo - FIFO state variables
20 * @on: reference counter for FIFO on.
21 * @en: bits field of INV_ICM42600_SENSOR_* for FIFO EN bits.
22 * @period: FIFO internal period.
23 * @watermark: watermark configuration values for accel and gyro.
24 * @count: number of bytes in the FIFO data buffer.
25 * @nb: gyro, accel and total samples in the FIFO data buffer.
26 * @data: FIFO data buffer aligned for DMA (2kB + 32 bytes of read cache).
35 } watermark; member
[all …]
Dinv_icm42600.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
67 /* ODR suffixed by LN or LP are Low-Noise or Low-Power mode only */
86 /* Low-Noise mode sensor data filter (3rd order filter by default) */
89 /* Low-Power mode sensor data filter (averaging) */
100 #define INV_ICM42600_SENSOR_CONF_INIT {-1, -1, -1, -1}
115 * struct inv_icm42600_state - driver state variables
127 * @buffer: data transfer buffer aligned for DMA.
128 * @fifo: FIFO management structure.
144 struct inv_icm42600_fifo fifo; member
188 /* all sensor data are 16 bits (2 registers wide) in big-endian */
[all …]
/kernel/linux/linux-4.19/drivers/net/wireless/intel/iwlwifi/fw/api/
Dsf.h8 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
31 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
32 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
66 /* Smart Fifo state */
75 /* Smart Fifo possible scenario */
88 /* smart FIFO default values */
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/intel/iwlwifi/fw/api/
Dsf.h8 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
31 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
32 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
66 /* Smart Fifo state */
75 /* Smart Fifo possible scenario */
88 /* smart FIFO default values */
[all …]
/kernel/linux/linux-5.10/drivers/iio/imu/st_lsm6dsx/
Dst_lsm6dsx_buffer.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * STMicroelectronics st_lsm6dsx FIFO buffer library driver
5 * LSM6DS3/LSM6DS3H/LSM6DSL/LSM6DSM/ISM330DLC/LSM6DS3TR-C:
6 * The FIFO buffer can be configured to store data from gyroscope and
8 * specific pattern based on 'FIFO data sets' (6 bytes each):
9 * - 1st data set is reserved for gyroscope data
10 * - 2nd data set is reserved for accelerometer data
11 * The FIFO pattern changes depending on the ODRs and decimation factors
12 * assigned to the FIFO data sets. The first sequence of data stored in FIFO
13 * buffer contains the data of all the enabled FIFO data sets
[all …]
/kernel/linux/linux-5.10/arch/powerpc/platforms/512x/
Dmpc512x_lpbfifo.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * The driver for Freescale MPC512x LocalPlus Bus FIFO
6 * Copyright (C) 2013-2015 Alexander Popov <alex.popov@linux.com>.
21 #include <linux/dma-direction.h>
22 #include <linux/dma-mapping.h>
61 * mpc512x_lpbfifo_irq - IRQ handler for LPB FIFO
76 if (!req || req->dir == MPC512X_LPBFIFO_REQ_DIR_READ) { in mpc512x_lpbfifo_irq()
81 status = in_be32(&lpbfifo.regs->status); in mpc512x_lpbfifo_irq()
84 out_be32(&lpbfifo.regs->enable, in mpc512x_lpbfifo_irq()
89 out_be32(&lpbfifo.regs->status, MPC512X_SCLPC_SUCCESS); in mpc512x_lpbfifo_irq()
[all …]
/kernel/linux/linux-4.19/arch/powerpc/platforms/512x/
Dmpc512x_lpbfifo.c2 * The driver for Freescale MPC512x LocalPlus Bus FIFO
5 * Copyright (C) 2013-2015 Alexander Popov <alex.popov@linux.com>.
22 #include <linux/dma-direction.h>
23 #include <linux/dma-mapping.h>
62 * mpc512x_lpbfifo_irq - IRQ handler for LPB FIFO
77 if (!req || req->dir == MPC512X_LPBFIFO_REQ_DIR_READ) { in mpc512x_lpbfifo_irq()
82 status = in_be32(&lpbfifo.regs->status); in mpc512x_lpbfifo_irq()
85 out_be32(&lpbfifo.regs->enable, in mpc512x_lpbfifo_irq()
90 out_be32(&lpbfifo.regs->status, MPC512X_SCLPC_SUCCESS); in mpc512x_lpbfifo_irq()
97 /* Transfer is finished, set the FIFO as idle */ in mpc512x_lpbfifo_irq()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/mcde/
Dmcde_display.c1 // SPDX-License-Identifier: GPL-2.0
5 * (C) ST-Ericsson SA 2013
9 #include <linux/dma-buf.h>
28 /* TODO: implement FIFO C0 and FIFO C1 */
72 mispp = readl(mcde->regs + MCDE_MISPP); in mcde_display_irq()
73 misovl = readl(mcde->regs + MCDE_MISOVL); in mcde_display_irq()
74 mischnl = readl(mcde->regs + MCDE_MISCHNL); in mcde_display_irq()
84 if (mcde_dsi_irq(mcde->mdsi)) { in mcde_display_irq()
93 if (mcde->flow_mode == MCDE_COMMAND_ONESHOT_FLOW) { in mcde_display_irq()
94 spin_lock(&mcde->flow_lock); in mcde_display_irq()
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/zte/
Dzx296718.dtsi5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/input/input.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/gpio/gpio.h>
47 #include <dt-bindings/clock/zx296718-clock.h>
51 #address-cells = <1>;
52 #size-cells = <1>;
53 interrupt-parent = <&gic>;
67 #address-cells = <2>;
68 #size-cells = <0>;
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/zte/
Dzx296718.dtsi5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/input/input.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/gpio/gpio.h>
47 #include <dt-bindings/clock/zx296718-clock.h>
51 #address-cells = <1>;
52 #size-cells = <1>;
53 interrupt-parent = <&gic>;
67 #address-cells = <2>;
68 #size-cells = <0>;
[all …]
/kernel/linux/linux-5.10/Documentation/ABI/testing/
Dsysfs-bus-iio3 Contact: linux-iio@vger.kernel.org
11 Contact: linux-iio@vger.kernel.org
25 Contact: linux-iio@vger.kernel.org
31 Contact: linux-iio@vger.kernel.org
38 Contact: linux-iio@vger.kernel.org
48 Contact: linux-iio@vger.kernel.org
65 Contact: linux-iio@vger.kernel.org
70 - a small discrete set of values like "0 2 4 6 8"
71 - a range with minimum, step and maximum frequencies like
76 Contact: linux-iio@vger.kernel.org
[all …]
/kernel/linux/linux-4.19/Documentation/ABI/testing/
Dsysfs-bus-iio3 Contact: linux-iio@vger.kernel.org
11 Contact: linux-iio@vger.kernel.org
24 Contact: linux-iio@vger.kernel.org
30 Contact: linux-iio@vger.kernel.org
37 Contact: linux-iio@vger.kernel.org
46 Contact: linux-iio@vger.kernel.org
62 Contact: linux-iio@vger.kernel.org
69 Contact: linux-iio@vger.kernel.org
76 Contact: linux-iio@vger.kernel.org
85 Contact: linux-iio@vger.kernel.org
[all …]
/kernel/linux/linux-5.10/drivers/net/usb/
Dsmsc95xx.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 2007-2008 SMSC
38 /* SCSRs - System Control and Status Registers */
57 #define INT_STS_TDFU_ (0x00002000) /* TX Data FIFO Underrun */
58 #define INT_STS_TDFO_ (0x00001000) /* TX Data FIFO Overrun */
65 #define RX_FIFO_FLUSH_ (0x00000001) /* Receive FIFO Flush */
71 #define TX_CFG_FIFO_FLUSH_ (0x00000001) /* Transmit FIFO Flush */
88 /* Receive FIFO Information Register */
90 #define RX_FIFO_INF_USED_ (0x0000FFFF) /* RX Data FIFO Used Space */
92 /* Transmit FIFO Information Register */
[all …]
/kernel/linux/linux-4.19/drivers/net/usb/
Dsmsc95xx.h3 * Copyright (C) 2007-2008 SMSC
50 /* SCSRs - System Control and Status Registers */
69 #define INT_STS_TDFU_ (0x00002000) /* TX Data FIFO Underrun */
70 #define INT_STS_TDFO_ (0x00001000) /* TX Data FIFO Overrun */
77 #define RX_FIFO_FLUSH_ (0x00000001) /* Receive FIFO Flush */
83 #define TX_CFG_FIFO_FLUSH_ (0x00000001) /* Transmit FIFO Flush */
100 /* Receive FIFO Information Register */
102 #define RX_FIFO_INF_USED_ (0x0000FFFF) /* RX Data FIFO Used Space */
104 /* Transmit FIFO Information Register */
106 #define TX_FIFO_INF_FREE_ (0x0000FFFF) /* TX Data FIFO Free Space */
[all …]
/kernel/linux/linux-5.10/sound/soc/fsl/
Dfsl_dma.c1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
16 #include <linux/dma-mapping.h>
72 /** fsl_dma_private: p-substream DMA data
74 * Each substream has a 1-to-1 association with a DMA channel.
76 * The link[] array is first because it needs to be aligned on a 32-byte
120 * Since each link descriptor has a 32-bit byte count field, we set
121 * period_bytes_max to the largest 32-bit number. We also have no maximum
137 .period_bytes_max = (u32) -1,
139 .periods_max = (unsigned int) -1,
[all …]
/kernel/linux/linux-4.19/sound/soc/fsl/
Dfsl_dma.c6 * Copyright 2007-2010 Freescale Semiconductor, Inc.
20 #include <linux/dma-mapping.h>
76 /** fsl_dma_private: p-substream DMA data
78 * Each substream has a 1-to-1 association with a DMA channel.
80 * The link[] array is first because it needs to be aligned on a 32-byte
124 * Since each link descriptor has a 32-bit byte count field, we set
125 * period_bytes_max to the largest 32-bit number. We also have no maximum
141 .period_bytes_max = (u32) -1,
143 .periods_max = (unsigned int) -1,
159 * fsl_dma_update_pointers - update LD pointers to point to the next period
[all …]
/kernel/linux/linux-5.10/drivers/i2c/busses/
Di2c-fsi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * FSI-attached I2C master algorithm
71 /* watermark register */
189 u32 mode = I2C_MODE_ENHANCED, extended_status, watermark; in fsi_i2c_dev_init() local
193 rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_INT_MASK, &interrupt); in fsi_i2c_dev_init()
198 rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_MODE, &mode); in fsi_i2c_dev_init()
202 rc = fsi_i2c_read_reg(i2c->fsi, I2C_FSI_ESTAT, &extended_status); in fsi_i2c_dev_init()
206 i2c->fifo_size = FIELD_GET(I2C_ESTAT_FIFO_SZ, extended_status); in fsi_i2c_dev_init()
207 watermark = FIELD_PREP(I2C_WATERMARK_HI, in fsi_i2c_dev_init()
208 i2c->fifo_size - I2C_FIFO_HI_LVL); in fsi_i2c_dev_init()
[all …]
/kernel/linux/linux-4.19/drivers/i2c/busses/
Di2c-fsi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * FSI-attached I2C master algorithm
71 /* watermark register */
189 u32 mode = I2C_MODE_ENHANCED, extended_status, watermark; in fsi_i2c_dev_init() local
193 rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_INT_MASK, &interrupt); in fsi_i2c_dev_init()
198 rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_MODE, &mode); in fsi_i2c_dev_init()
202 rc = fsi_i2c_read_reg(i2c->fsi, I2C_FSI_ESTAT, &extended_status); in fsi_i2c_dev_init()
206 i2c->fifo_size = FIELD_GET(I2C_ESTAT_FIFO_SZ, extended_status); in fsi_i2c_dev_init()
207 watermark = FIELD_PREP(I2C_WATERMARK_HI, in fsi_i2c_dev_init()
208 i2c->fifo_size - I2C_FIFO_HI_LVL); in fsi_i2c_dev_init()
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/broadcom/
Db44.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 #define B44_BIST_STAT 0x000CUL /* Built-In Self-Test Status */
41 #define ISTAT_RFO 0x00004000 /* Receive FIFO Overflow */
42 #define ISTAT_TFU 0x00008000 /* Transmit FIFO Underflow */
65 #define MAC_FLOW_RX_HI_WATER 0x000000ff /* Receive FIFO HI Water Mark */
90 #define DMATX_STAT_EDFU 0x00020000 /* Error Data FIFO Underrun */
110 #define DMARX_STAT_EDFO 0x00020000 /* Error Data FIFO Overflow */
113 #define B44_DMAFIFO_AD 0x0220UL /* DMA FIFO Diag Address */
120 #define DMAFIFO_AD_SXFD 0x00080000 /* Select Transmit FIFO Data */
121 #define DMAFIFO_AD_SXFP 0x00090000 /* Select Transmit FIFO Pointers */
[all …]
/kernel/linux/linux-4.19/drivers/net/ethernet/broadcom/
Db44.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 #define B44_BIST_STAT 0x000CUL /* Built-In Self-Test Status */
41 #define ISTAT_RFO 0x00004000 /* Receive FIFO Overflow */
42 #define ISTAT_TFU 0x00008000 /* Transmit FIFO Underflow */
65 #define MAC_FLOW_RX_HI_WATER 0x000000ff /* Receive FIFO HI Water Mark */
90 #define DMATX_STAT_EDFU 0x00020000 /* Error Data FIFO Underrun */
110 #define DMARX_STAT_EDFO 0x00020000 /* Error Data FIFO Overflow */
113 #define B44_DMAFIFO_AD 0x0220UL /* DMA FIFO Diag Address */
120 #define DMAFIFO_AD_SXFD 0x00080000 /* Select Transmit FIFO Data */
121 #define DMAFIFO_AD_SXFP 0x00090000 /* Select Transmit FIFO Pointers */
[all …]

123