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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/net/
Dsmsc911x.txt1 * Smart Mixed-Signal Connectivity (SMSC) LAN911x/912x Controller
4 - compatible : Should be "smsc,lan<model>", "smsc,lan9115"
5 - reg : Address and length of the io space for SMSC LAN
6 - interrupts : one or two interrupt specifiers
7 - The first interrupt is the SMSC LAN interrupt line
8 - The second interrupt (if present) is the PME (power
11 - phy-mode : See ethernet.txt file in the same directory
14 - reg-shift : Specify the quantity to shift the register offsets by
15 - reg-io-width : Specify the size (in bytes) of the IO accesses that
18 - smsc,irq-active-high : Indicates the IRQ polarity is active-high
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dsmsc911x.txt1 * Smart Mixed-Signal Connectivity (SMSC) LAN911x/912x Controller
4 - compatible : Should be "smsc,lan<model>", "smsc,lan9115"
5 - reg : Address and length of the io space for SMSC LAN
6 - interrupts : one or two interrupt specifiers
7 - The first interrupt is the SMSC LAN interrupt line
8 - The second interrupt (if present) is the PME (power
11 - phy-mode : See ethernet.txt file in the same directory
14 - reg-shift : Specify the quantity to shift the register offsets by
15 - reg-io-width : Specify the size (in bytes) of the IO accesses that
18 - smsc,irq-active-high : Indicates the IRQ polarity is active-high
[all …]
/kernel/linux/linux-5.10/Documentation/networking/device_drivers/ethernet/davicom/
Ddm9000.rst1 .. SPDX-License-Identifier: GPL-2.0
9 Ben Dooks <ben@simtec.co.uk> <ben-linux@fluff.org>
13 ------------
15 This file describes how to use the DM9000 platform-device based network driver
25 ----------------------------
37 An example from arch/arm/mach-s3c2410/mach-bast.c is::
91 -------------
94 device, whether or not an external PHY is attached to the device and
113 The chip is connected to an external PHY.
122 Switch to using the simpler PHY polling method which does not
[all …]
/kernel/linux/linux-4.19/Documentation/networking/
Ddm9000.txt5 Ben Dooks <ben@simtec.co.uk> <ben-linux@fluff.org>
9 ------------
11 This file describes how to use the DM9000 platform-device based network driver
21 ----------------------------
33 An example from arch/arm/mach-s3c2410/mach-bast.c is:
87 -------------
90 device, whether or not an external PHY is attached to the device and
109 The chip is connected to an external PHY.
118 Switch to using the simpler PHY polling method which does not
119 try and read the MII PHY state regularly. This is only available
[all …]
Dstmmac.txt3 Copyright (C) 2007-2015 STMicroelectronics Ltd
6 This is the driver for the MAC 10/100/1000 on-chip Ethernet controllers
22 Device Drivers ---> Network device support ---> Ethernet (1000 Mbit) --->
30 phyaddr: to manually provide the physical address to the PHY device;
50 net_device structure, enabling the scatter-gather feature. This is true on
62 The incoming packets are stored, by the DMA, in a list of pre-allocated socket
63 buffers in order to avoid the memcpy (zero-copy).
68 New chips have an HW RX-Watchdog used for this mitigation.
80 and linked-list(CHAINED) mode. In RING each descriptor points to two
99 For example, driver statistics (including RMON), internal errors can be taken
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-omap2/
Domap_phy_internal.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * This file configures the internal USB PHY in OMAP4430. Used
6 * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com
28 * omap4430_phy_power_down: disable MUSB PHY during early init
30 * OMAP4 MUSB PHY module is enabled by default on reset, but this will
44 return -ENOMEM; in omap4430_phy_power_down()
47 /* Power down the phy */ in omap4430_phy_power_down()
79 * Start the on-chip PHY and its PLL. in am35x_musb_phy_power()
88 pr_info("Waiting for PHY clock good...\n"); in am35x_musb_phy_power()
94 pr_err("musb PHY clock good timed out\n"); in am35x_musb_phy_power()
[all …]
/kernel/linux/linux-4.19/arch/arm/mach-omap2/
Domap_phy_internal.c2 * This file configures the internal USB PHY in OMAP4430. Used
5 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
42 * omap4430_phy_power_down: disable MUSB PHY during early init
44 * OMAP4 MUSB PHY module is enabled by default on reset, but this will
58 return -ENOMEM; in omap4430_phy_power_down()
61 /* Power down the phy */ in omap4430_phy_power_down()
93 * Start the on-chip PHY and its PLL. in am35x_musb_phy_power()
102 pr_info("Waiting for PHY clock good...\n"); in am35x_musb_phy_power()
108 pr_err("musb PHY clock good timed out\n"); in am35x_musb_phy_power()
114 * Power down the on-chip PHY. in am35x_musb_phy_power()
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/kernel/linux/linux-4.19/arch/mips/include/asm/mach-bcm63xx/
Dbcm63xx_dev_enet.h1 /* SPDX-License-Identifier: GPL-2.0 */
21 /* or fill phy info to use an external one */
26 /* if has_phy, use autonegotiated pause parameters or force
50 /* DMA engine has internal SRAM */
68 #define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
69 #define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
98 /* DMA engine has internal SRAM */
/kernel/linux/linux-5.10/arch/mips/include/asm/mach-bcm63xx/
Dbcm63xx_dev_enet.h1 /* SPDX-License-Identifier: GPL-2.0 */
21 /* or fill phy info to use an external one */
26 /* if has_phy, use autonegotiated pause parameters or force
50 /* DMA engine has internal SRAM */
68 #define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
69 #define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
98 /* DMA engine has internal SRAM */
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/mmc/
Darasan,sdhci.txt3 The bindings follow the mmc[1], clock[2], interrupt[3] and phy[4] bindings.
7 [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
9 [4] Documentation/devicetree/bindings/phy/phy-bindings.txt
12 - compatible: Compatibility string. One of:
13 - "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY
14 - "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY
15 - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY
16 - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY
17 For this device it is strongly suggested to include arasan,soc-ctl-syscon.
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/kernel/linux/linux-5.10/drivers/net/ethernet/intel/ixgbe/
Dixgbe_x550.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
17 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_get_invariants_X550_x()
18 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_get_invariants_X550_x() local
19 struct ixgbe_link_info *link = &hw->link; in ixgbe_get_invariants_X550_x()
24 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) in ixgbe_get_invariants_X550_x()
25 phy->ops.set_phy_power = NULL; in ixgbe_get_invariants_X550_x()
27 link->addr = IXGBE_CS4227; in ixgbe_get_invariants_X550_x()
34 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_get_invariants_X550_x_fw() local
39 phy->ops.set_phy_power = NULL; in ixgbe_get_invariants_X550_x_fw()
[all …]
/kernel/linux/linux-4.19/drivers/net/ethernet/intel/ixgbe/
Dixgbe_x550.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
17 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_get_invariants_X550_x()
18 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_get_invariants_X550_x() local
19 struct ixgbe_link_info *link = &hw->link; in ixgbe_get_invariants_X550_x()
24 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) in ixgbe_get_invariants_X550_x()
25 phy->ops.set_phy_power = NULL; in ixgbe_get_invariants_X550_x()
27 link->addr = IXGBE_CS4227; in ixgbe_get_invariants_X550_x()
34 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_get_invariants_X550_x_fw() local
39 phy->ops.set_phy_power = NULL; in ixgbe_get_invariants_X550_x_fw()
[all …]
/kernel/linux/linux-5.10/drivers/phy/
Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
11 * The first PLL clock macro is used for internal reference clock. The second
12 * PLL clock macro is used to generate the clock for the PHY. This driver
13 * configures the first PLL CMU, the second PLL CMU, and programs the PHY to
15 * required if internal clock is enabled.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
[all …]
/kernel/linux/linux-4.19/drivers/phy/
Dphy-xgene.c2 * AppliedMicro X-Gene Multi-purpose PHY driver
22 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
23 * The first PLL clock macro is used for internal reference clock. The second
24 * PLL clock macro is used to generate the clock for the PHY. This driver
25 * configures the first PLL CMU, the second PLL CMU, and programs the PHY to
27 * required if internal clock is enabled.
31 * -----------------
32 * | Internal | |------|
33 * | Ref PLL CMU |----| | ------------- ---------
34 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
[all …]
/kernel/linux/linux-5.10/drivers/net/phy/
Dbcm7xxx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Broadcom BCM7xxx internal transceivers support.
5 * Copyright (C) 2014-2017 Broadcom
9 #include <linux/phy.h>
11 #include "bcm-phy-lib.h"
17 /* Broadcom BCM7xxx internal PHY registers */
59 /* AFE_RXCONFIG_2, set rCal offset for HT=0 code and LT=-2 code */ in bcm7xxx_28nm_d0_afe_config_init()
74 /* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal in bcm7xxx_28nm_d0_afe_config_init()
79 /* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */ in bcm7xxx_28nm_d0_afe_config_init()
102 /* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal in bcm7xxx_28nm_e0_plus_afe_config_init()
[all …]
Dbroadcom.c1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/net/phy/broadcom.c
13 #include "bcm-phy-lib.h"
15 #include <linux/phy.h>
20 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
23 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
25 MODULE_DESCRIPTION("Broadcom PHY driver");
33 /* handling PHY's internal RX clock delay */ in bcm54xx_config_clock_delay()
36 if (phydev->interface == PHY_INTERFACE_MODE_RGMII || in bcm54xx_config_clock_delay()
37 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { in bcm54xx_config_clock_delay()
[all …]
/kernel/linux/linux-4.19/drivers/net/dsa/
Dbcm_sf2.c17 #include <linux/phy.h>
68 if (priv->type == BCM7445_DEVICE_ID) in bcm_sf2_imp_setup()
73 /* Force link status for IMP port */ in bcm_sf2_imp_setup()
112 /* Use PHY-driven LED signaling */ in bcm_sf2_gphy_enable_set()
165 struct phy_device *phy) in bcm_sf2_port_setup() argument
182 if (priv->brcm_tag_mask & BIT(port)) in bcm_sf2_port_setup()
193 /* Re-enable the GPHY and re-apply workarounds */ in bcm_sf2_port_setup()
194 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) { in bcm_sf2_port_setup()
196 if (phy) { in bcm_sf2_port_setup()
197 /* if phy_stop() has been called before, phy in bcm_sf2_port_setup()
[all …]
/kernel/linux/linux-4.19/drivers/net/phy/
Dbcm7xxx.c2 * Broadcom BCM7xxx internal transceivers support.
4 * Copyright (C) 2014-2017 Broadcom
13 #include <linux/phy.h>
15 #include "bcm-phy-lib.h"
20 /* Broadcom BCM7xxx internal PHY registers */
89 /* Adjust bias current trim by -3 */ in bcm7xxx_28nm_b0_afe_config_init()
123 /* AFE_RXCONFIG_2, set rCal offset for HT=0 code and LT=-2 code */ in bcm7xxx_28nm_d0_afe_config_init()
138 /* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal in bcm7xxx_28nm_d0_afe_config_init()
143 /* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */ in bcm7xxx_28nm_d0_afe_config_init()
166 /* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal in bcm7xxx_28nm_e0_plus_afe_config_init()
[all …]
Dbroadcom.c2 * drivers/net/phy/broadcom.c
17 #include "bcm-phy-lib.h"
19 #include <linux/phy.h>
24 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
27 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
29 MODULE_DESCRIPTION("Broadcom PHY driver");
46 if (phydev->dev_flags & PHY_BRCM_EN_MASTER_MODE) { in bcm54210e_config_init()
59 /* Clear TX internal delay unless requested. */ in bcm54612e_config_init()
60 if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) && in bcm54612e_config_init()
61 (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) { in bcm54612e_config_init()
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Ds3c6410-smdk6410.dts1 // SPDX-License-Identifier: GPL-2.0
11 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
31 fin_pll: oscillator-0 {
32 compatible = "fixed-clock";
33 clock-frequency = <12000000>;
34 clock-output-names = "fin_pll";
35 #clock-cells = <0>;
38 xusbxti: oscillator-1 {
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Ds3c6410-smdk6410.dts1 // SPDX-License-Identifier: GPL-2.0
11 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
32 compatible = "simple-bus";
33 #address-cells = <1>;
34 #size-cells = <0>;
37 compatible = "fixed-clock";
39 clock-frequency = <12000000>;
40 clock-output-names = "fin_pll";
[all …]
Dexynos5410-smdk5410.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/irq.h>
26 compatible = "fixed-clock";
27 clock-frequency = <24000000>;
28 clock-output-names = "fin_pll";
29 #clock-cells = <0>;
33 compatible = "samsung,secure-firmware";
41 cap-mmc-highspeed;
42 broken-cd;
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/memory-controllers/
Dexynos-srom.txt4 - compatible : Should contain "samsung,exynos4210-srom".
6 - reg: offset and length of the register set
12 - #address-cells: Must be set to 2 to allow device address translation.
15 - #size-cells: Must be set to 1 to allow device size passing
17 - ranges: Must be set up to reflect the memory layout with four integer values
19 <bank-number> 0 <parent address of bank> <size>
21 Sub-nodes:
27 - reg: bank number, base address (relative to start of the bank) and size of
31 - samsung,srom-timing : array of 6 integers, specifying bank timings in the
35 Tacp : Page mode access cycle at Page mode (0 - 15)
[all …]
/kernel/linux/linux-5.10/Documentation/networking/device_drivers/ethernet/stmicro/
Dstmmac.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
35 DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores
[all …]
/kernel/linux/linux-4.19/drivers/mmc/host/
Dsdhci-xenon.c7 * Date: 2016-8-24
24 #include "sdhci-pltfm.h"
25 #include "sdhci-xenon.h"
44 dev_err(mmc_dev(host->mmc), "Internal clock never stabilised.\n"); in xenon_enable_internal_clk()
45 return -ETIMEDOUT; in xenon_enable_internal_clk()
53 /* Set SDCLK-off-while-idle */
94 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; in xenon_enable_sdhc()
96 * Force to clear BUS_TEST to in xenon_enable_sdhc()
99 host->mmc->caps &= ~MMC_CAP_BUS_WIDTH_TEST; in xenon_enable_sdhc()
140 /* Disable the Re-Tuning Request functionality */ in xenon_retune_setup()
[all …]

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