| /kernel/linux/linux-5.10/drivers/net/phy/ |
| D | phy-core.c | 1 // SPDX-License-Identifier: GPL-2.0+
10 * phy_speed_to_str - Return a string representing the PHY link speed
55 return "Unsupported (update phy-core.c)"; in phy_speed_to_str()
61 * phy_duplex_to_str - Return string describing the duplex
70 return "Full"; in phy_duplex_to_str()
73 return "Unsupported (update phy-core.c)"; in phy_duplex_to_str()
79 * - iow, descending speed. */
82 .bit = ETHTOOL_LINK_MODE_ ## b ## _BIT}
86 PHY_SETTING( 400000, FULL, 400000baseCR8_Full ),
87 PHY_SETTING( 400000, FULL, 400000baseKR8_Full ),
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| /kernel/linux/linux-5.10/drivers/acpi/acpica/ |
| D | utmath.c | 1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
4 * Module Name: utmath - Integer math support routines
14 /* Structures used only for 64-bit divide */
22 u64 full; member
28 * Optional support for 64-bit double-precision integer multiply and shift.
29 * This code is configurable and is implemented in order to support 32-bit
30 * kernel environments where a 64-bit double-precision math library is not
39 * PARAMETERS: multiplicand - 64-bit multiplicand
40 * multiplier - 32-bit multiplier
41 * out_product - Pointer to where the product is returned
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| /kernel/linux/linux-4.19/drivers/acpi/acpica/ |
| D | utmath.c | 1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
4 * Module Name: utmath - Integer math support routines
14 /* Structures used only for 64-bit divide */
22 u64 full; member
28 * Optional support for 64-bit double-precision integer multiply and shift.
29 * This code is configurable and is implemented in order to support 32-bit
30 * kernel environments where a 64-bit double-precision math library is not
39 * PARAMETERS: multiplicand - 64-bit multiplicand
40 * multiplier - 32-bit multiplier
41 * out_product - Pointer to where the product is returned
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| /kernel/linux/linux-5.10/drivers/staging/comedi/drivers/ |
| D | jr3_pci.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
4 * is 16 bits, but aligned on a 32 bit PCI boundary
31 * two-byte words.
42 * Channels 1-6 contain the coupled force data Fx through Mz. Channel
43 * 7 contains the sensor's calibration data. The use of channels 8-15
70 * the full scales.
84 * which axes to use in computing the vectors. Each bit signifies
85 * selection of a single axis. The V1x axis bit corresponds to a hex
86 * value of 0x0001 and the V2z bit corresponds to a hex value of
91 * calculated. Setting the changeV1 bit or the changeV2 bit will
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| /kernel/linux/linux-4.19/drivers/staging/comedi/drivers/ |
| D | jr3_pci.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
4 * is 16 bits, but aligned on a 32 bit PCI boundary
31 * two-byte words.
42 * Channels 1-6 contain the coupled force data Fx through Mz. Channel
43 * 7 contains the sensor's calibration data. The use of channels 8-15
70 * the full scales.
84 * which axes to use in computing the vectors. Each bit signifies
85 * selection of a single axis. The V1x axis bit corresponds to a hex
86 * value of 0x0001 and the V2z bit corresponds to a hex value of
91 * calculated. Setting the changeV1 bit or the changeV2 bit will
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|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/ |
| D | st,stm32-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 DMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a four-cell specifier for each
17 3. A 32bit mask specifying the DMA channel configuration which are device
19 -bit 9: Peripheral Increment Address
22 -bit 10: Memory Increment Address
25 -bit 15: Peripheral Increment Offset Size
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/dma/ |
| D | stm32-dma.txt | 3 The STM32 DMA is a general-purpose direct memory access controller capable of
7 - compatible: Should be "st,stm32-dma"
8 - reg: Should contain DMA registers location and length. This should include
9 all of the per-channel registers.
10 - interrupts: Should contain all of the per-channel DMA interrupts in
12 - clocks: Should contain the input clock of the DMA instance.
13 - #dma-cells : Must be <4>. See DMA client paragraph for more details.
16 - dma-requests : Number of DMA requests supported.
17 - resets: Reference to a reset controller asserting the DMA controller
18 - st,mem2mem: boolean; if defined, it indicates that the controller supports
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| /kernel/linux/linux-4.19/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac1000.h | 2 Copyright (C) 2007-2009 STMicroelectronics Ltd
13 The full GNU General Public License is included in this distribution in
33 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
36 #define GMAC_INT_STATUS_PMT BIT(3)
37 #define GMAC_INT_STATUS_MMCIS BIT(4)
38 #define GMAC_INT_STATUS_MMCRIS BIT(5)
39 #define GMAC_INT_STATUS_MMCTIS BIT(6)
40 #define GMAC_INT_STATUS_MMCCSUM BIT(7)
41 #define GMAC_INT_STATUS_TSTAMP BIT(9)
42 #define GMAC_INT_STATUS_LPIIS BIT(10)
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| /kernel/linux/linux-5.10/include/linux/ |
| D | cnt32_to_63.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Extend a 32-bit counter to 63 bits
31 * cnt32_to_63 - Expand a 32-bit counter to a 63-bit counter
35 * a relatively short period making wrap-arounds rather frequent. This
36 * is a problem when implementing sched_clock() for example, where a 64-bit
37 * non-wrapping monotonic value is expected to be returned.
39 * To overcome that limitation, let's extend a 32-bit counter to 63 bits
41 * by the hardware while bits 32 to 62 are stored in memory. The top bit in
42 * memory is used to synchronize with the hardware clock half-period. When
43 * the top bit of both counters (hardware and in memory) differ then the
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| /kernel/linux/linux-4.19/include/linux/ |
| D | cnt32_to_63.h | 2 * Extend a 32-bit counter to 63 bits
34 * cnt32_to_63 - Expand a 32-bit counter to a 63-bit counter
38 * a relatively short period making wrap-arounds rather frequent. This
39 * is a problem when implementing sched_clock() for example, where a 64-bit
40 * non-wrapping monotonic value is expected to be returned.
42 * To overcome that limitation, let's extend a 32-bit counter to 63 bits
44 * by the hardware while bits 32 to 62 are stored in memory. The top bit in
45 * memory is used to synchronize with the hardware clock half-period. When
46 * the top bit of both counters (hardware and in memory) differ then the
51 * always be in synch with the top bit indicating to any potential concurrent
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| /kernel/linux/linux-5.10/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac1000.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 Copyright (C) 2007-2009 STMicroelectronics Ltd
23 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
26 #define GMAC_INT_STATUS_PMT BIT(3)
27 #define GMAC_INT_STATUS_MMCIS BIT(4)
28 #define GMAC_INT_STATUS_MMCRIS BIT(5)
29 #define GMAC_INT_STATUS_MMCTIS BIT(6)
30 #define GMAC_INT_STATUS_MMCCSUM BIT(7)
31 #define GMAC_INT_STATUS_TSTAMP BIT(9)
32 #define GMAC_INT_STATUS_LPIIS BIT(10)
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| /kernel/linux/linux-5.10/include/asm-generic/bitops/ |
| D | instrumented-atomic.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
4 * This file provides wrappers with sanitizer instrumentation for atomic bit
8 * the below bit operations with an arch_ prefix (e.g. arch_set_bit(),
17 * set_bit - Atomically set a bit in memory
18 * @nr: the bit to set
24 * restricted to acting on a single-word quantity.
33 * clear_bit - Clears a bit in memory
34 * @nr: Bit to clear
46 * change_bit - Toggle a bit in memory
47 * @nr: Bit to change
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| /kernel/linux/linux-4.19/drivers/spi/ |
| D | spi-meson-spicc.c | 7 * SPDX-License-Identifier: GPL-2.0+
29 * - all transfers are cutted in 16 words burst because the FIFO hangs on
30 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
32 * - CS management is dumb, and goes UP between every burst, so is really a
34 * to have a CS go down over the full transfer
46 #define SPICC_ENABLE BIT(0)
47 #define SPICC_MODE_MASTER BIT(1)
48 #define SPICC_XCH BIT(2)
49 #define SPICC_SMC BIT(3)
50 #define SPICC_POL BIT(4)
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| /kernel/linux/linux-4.19/kernel/rcu/ |
| D | Kconfig | 2 # RCU-related configuration options
22 thousands of CPUs, but for which real-time response
33 designed for UP systems from which real-time response
38 bool "Make expert-level adjustments to RCU configuration"
42 expert-level adjustments to RCU configuration. By default,
43 no such adjustments can be made, which has the often-beneficial
44 side-effect of preventing "make oldconfig" from asking you all
48 Say Y if you need to make expert-level adjustments to RCU.
56 permits arbitrary sleeping or blocking within RCU read-side critical
63 This option selects the single-CPU non-preemptible version of SRCU.
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| /kernel/linux/linux-5.10/drivers/hyperhold/ |
| D | hp_space.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2020-2022 Huawei Technologies Co., Ltd.
23 kvfree(spc->bitmap); in deinit_space()
24 atomic64_sub(BITS_TO_LONGS(spc->nr_ext) * sizeof(long), &spc_mem); in deinit_space()
25 spc->ext_size = 0; in deinit_space()
26 spc->nr_ext = 0; in deinit_space()
27 atomic_set(&spc->last_alloc_bit, 0); in deinit_space()
28 atomic_set(&spc->nr_alloced, 0); in deinit_space()
35 if (ext_size & (PAGE_SIZE - 1)) { in init_space()
39 if (dev_size & (ext_size - 1)) { in init_space()
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|
| /kernel/linux/linux-4.19/Documentation/hwmon/ |
| D | vt1211 | 7 Addresses scanned: none, address read from Super-I/O config space
20 -----------------
23 configuration for channels 1-5.
24 Legal values are in the range of 0-31. Bit 0 maps to
25 UCH1, bit 1 maps to UCH2 and so on. Setting a bit to 1
27 setting a bit to 0 enables the voltage input.
40 -----------
42 The VIA VT1211 Super-I/O chip includes complete hardware monitoring
45 implements 5 universal input channels (UCH1-5) that can be individually
53 connected to the PWM outputs of the VT1211 :-().
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|
| /kernel/linux/linux-4.19/drivers/scsi/ |
| D | aha1542.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 #define STST BIT(7) /* Self Test in Progress */
11 #define DIAGF BIT(6) /* Internal Diagnostic Failure */
12 #define INIT BIT(5) /* Mailbox Initialization Required */
13 #define IDLE BIT(4) /* SCSI Host Adapter Idle */
14 #define CDF BIT(3) /* Command/Data Out Port Full */
15 #define DF BIT(2) /* Data In Port Full */
16 /* BIT(1) is reserved */
17 #define INVDCMD BIT(0) /* Invalid H A Command */
21 #define ANYINTR BIT(7) /* Any Interrupt */
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| /kernel/linux/linux-5.10/drivers/scsi/ |
| D | aha1542.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 #define STST BIT(7) /* Self Test in Progress */
11 #define DIAGF BIT(6) /* Internal Diagnostic Failure */
12 #define INIT BIT(5) /* Mailbox Initialization Required */
13 #define IDLE BIT(4) /* SCSI Host Adapter Idle */
14 #define CDF BIT(3) /* Command/Data Out Port Full */
15 #define DF BIT(2) /* Data In Port Full */
16 /* BIT(1) is reserved */
17 #define INVDCMD BIT(0) /* Invalid H A Command */
21 #define ANYINTR BIT(7) /* Any Interrupt */
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|
| /kernel/linux/linux-5.10/drivers/spi/ |
| D | spi-meson-spicc.c | 7 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/clk-provider.h>
30 * - all transfers are cutted in 16 words burst because the FIFO hangs on
31 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
33 * - CS management is dumb, and goes UP between every burst, so is really a
35 * to have a CS go down over the full transfer
46 #define SPICC_ENABLE BIT(0)
47 #define SPICC_MODE_MASTER BIT(1)
48 #define SPICC_XCH BIT(2)
49 #define SPICC_SMC BIT(3)
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|
| /kernel/linux/linux-4.19/drivers/hwtracing/coresight/ |
| D | coresight-tmc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/dma-mapping.h>
41 /* TMC_CTL - 0x020 */
42 #define TMC_CTL_CAPT_EN BIT(0)
43 /* TMC_STS - 0x00C */
45 #define TMC_STS_FULL BIT(0)
46 #define TMC_STS_TRIGGERED BIT(1)
48 * TMC_AXICTL - 0x110
50 * TMC AXICTL format for SoC-400
51 * Bits [0-1] : ProtCtrlBit0-1
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|
| /kernel/liteos_m/arch/risc-v/nuclei/gcc/nmsis/Core/Include/ |
| D | core_feature_base.h | 4 * SPDX-License-Identifier: Apache-2.0
10 * www.apache.org/licenses/LICENSE-2.0
47 /** \brief Type of Control and Status Register(CSR), depends on the XLEN defined in RISC-V */
68 rv_csr_t a:1; /*!< bit: 0 Atomic extension */
69 …rv_csr_t b:1; /*!< bit: 1 Tentatively reserved for Bit-Manipulation…
70 rv_csr_t c:1; /*!< bit: 2 Compressed extension */
71 …rv_csr_t d:1; /*!< bit: 3 Double-precision floating-point extension…
72 rv_csr_t e:1; /*!< bit: 4 RV32E base ISA */
73 …rv_csr_t f:1; /*!< bit: 5 Single-precision floating-point extension…
74 … rv_csr_t g:1; /*!< bit: 6 Additional standard extensions present */
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|
| /kernel/linux/linux-4.19/arch/m68k/include/asm/ |
| D | mcfuart.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * mcfuart.h -- ColdFire internal UART support defines.
7 * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
52 #define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */
53 #define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */
57 * Define bit flags in Mode Register 1 (MR1).
60 #define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */
77 * Define bit flags in Mode Register 2 (MR2).
85 #define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */
90 * Define bit flags in Status Register (USR).
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| /kernel/linux/linux-5.10/arch/m68k/include/asm/ |
| D | mcfuart.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * mcfuart.h -- ColdFire internal UART support defines.
7 * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
52 #define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */
53 #define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */
57 * Define bit flags in Mode Register 1 (MR1).
60 #define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */
77 * Define bit flags in Mode Register 2 (MR2).
85 #define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */
90 * Define bit flags in Status Register (USR).
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|
| /kernel/linux/linux-5.10/arch/x86/include/asm/ |
| D | perf_event.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
120 unsigned int full; member
133 unsigned int full; member
144 unsigned int full; member
155 /* Deep C-state Reset */
160 unsigned int full; member
169 /* Call-stack Mode Supported */
172 unsigned int full; member
177 /* Mispredict Bit Supported */
184 unsigned int full; member
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| /kernel/linux/linux-4.19/Documentation/admin-guide/hw-vuln/ |
| D | tsx_async_abort.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 TAA - TSX Asynchronous Abort
11 -------------------
14 Transactional Synchronization Extensions (TSX) when the TAA_NO bit (bit 8)
15 is 0 in the IA32_ARCH_CAPABILITIES MSR. On processors where the MDS_NO bit
16 (bit 5) is 0 in the IA32_ARCH_CAPABILITIES MSR, the existing MDS mitigations
23 ------------
28 CVE-2019-11135 TAA TSX Asynchronous Abort (TAA) condition on some
36 -------
43 hardware transactional memory support to improve performance of multi-threaded
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|