| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_gfx.c | 31 /* delay 0.1 second to enable gfx off feature */
35 * GPU GFX IP block helpers function.
43 bit += mec * adev->gfx.mec.num_pipe_per_mec in amdgpu_gfx_mec_queue_to_bit()
44 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
45 bit += pipe * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
54 *queue = bit % adev->gfx.mec.num_queue_per_pipe; in amdgpu_queue_mask_bit_to_mec_queue()
55 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
56 % adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
57 *mec = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
58 / adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
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| D | amdgpu_rlc.c | 39 if (adev->gfx.rlc.in_safe_mode) in amdgpu_gfx_rlc_enter_safe_mode()
43 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_enter_safe_mode()
49 adev->gfx.rlc.funcs->set_safe_mode(adev); in amdgpu_gfx_rlc_enter_safe_mode()
50 adev->gfx.rlc.in_safe_mode = true; in amdgpu_gfx_rlc_enter_safe_mode()
63 if (!(adev->gfx.rlc.in_safe_mode)) in amdgpu_gfx_rlc_exit_safe_mode()
67 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_exit_safe_mode()
73 adev->gfx.rlc.funcs->unset_safe_mode(adev); in amdgpu_gfx_rlc_exit_safe_mode()
74 adev->gfx.rlc.in_safe_mode = false; in amdgpu_gfx_rlc_exit_safe_mode()
97 &adev->gfx.rlc.save_restore_obj, in amdgpu_gfx_rlc_init_sr()
98 &adev->gfx.rlc.save_restore_gpu_addr, in amdgpu_gfx_rlc_init_sr()
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| D | gfx_v6_0.c | 341 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v6_0_init_microcode()
344 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v6_0_init_microcode()
347 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v6_0_init_microcode()
348 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
349 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
352 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v6_0_init_microcode()
355 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v6_0_init_microcode()
358 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v6_0_init_microcode()
359 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
360 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
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| D | gfx_v7_0.c | 930 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
933 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v7_0_init_microcode()
938 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
941 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v7_0_init_microcode()
946 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
949 err = amdgpu_ucode_validate(adev->gfx.ce_fw); in gfx_v7_0_init_microcode()
954 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
957 err = amdgpu_ucode_validate(adev->gfx.mec_fw); in gfx_v7_0_init_microcode()
963 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
966 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); in gfx_v7_0_init_microcode()
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| D | gfx_v8_0.c | 831 adev->gfx.scratch.num_reg = 8; in gfx_v8_0_scratch_init()
832 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; in gfx_v8_0_scratch_init()
833 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v8_0_scratch_init()
932 release_firmware(adev->gfx.pfp_fw); in gfx_v8_0_free_microcode()
933 adev->gfx.pfp_fw = NULL; in gfx_v8_0_free_microcode()
934 release_firmware(adev->gfx.me_fw); in gfx_v8_0_free_microcode()
935 adev->gfx.me_fw = NULL; in gfx_v8_0_free_microcode()
936 release_firmware(adev->gfx.ce_fw); in gfx_v8_0_free_microcode()
937 adev->gfx.ce_fw = NULL; in gfx_v8_0_free_microcode()
938 release_firmware(adev->gfx.rlc_fw); in gfx_v8_0_free_microcode()
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| D | gfx_v9_0.c | 47 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
932 adev->gfx.kiq.pmf = &gfx_v9_0_kiq_pm4_funcs; in gfx_v9_0_set_kiq_pm4_funcs()
995 adev->gfx.scratch.num_reg = 8; in gfx_v9_0_scratch_init()
996 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v9_0_scratch_init()
997 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v9_0_scratch_init()
1130 release_firmware(adev->gfx.pfp_fw); in gfx_v9_0_free_microcode()
1131 adev->gfx.pfp_fw = NULL; in gfx_v9_0_free_microcode()
1132 release_firmware(adev->gfx.me_fw); in gfx_v9_0_free_microcode()
1133 adev->gfx.me_fw = NULL; in gfx_v9_0_free_microcode()
1134 release_firmware(adev->gfx.ce_fw); in gfx_v9_0_free_microcode()
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| D | gfx_v10_0.c | 42 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
3335 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; in gfx_v10_0_set_kiq_pm4_funcs()
3410 adev->gfx.scratch.num_reg = 8; in gfx_v10_0_scratch_init()
3411 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v10_0_scratch_init()
3412 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v10_0_scratch_init()
3551 release_firmware(adev->gfx.pfp_fw); in gfx_v10_0_free_microcode()
3552 adev->gfx.pfp_fw = NULL; in gfx_v10_0_free_microcode()
3553 release_firmware(adev->gfx.me_fw); in gfx_v10_0_free_microcode()
3554 adev->gfx.me_fw = NULL; in gfx_v10_0_free_microcode()
3555 release_firmware(adev->gfx.ce_fw); in gfx_v10_0_free_microcode()
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| D | amdgpu_discovery.c | 389 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->gc_num_se); in amdgpu_discovery_get_gfx_info()
390 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->gc_num_wgp0_per_sa) + in amdgpu_discovery_get_gfx_info()
392 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->gc_num_sa_per_se); in amdgpu_discovery_get_gfx_info()
393 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->gc_num_rb_per_se); in amdgpu_discovery_get_gfx_info()
394 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->gc_num_gl2c); in amdgpu_discovery_get_gfx_info()
395 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->gc_num_gprs); in amdgpu_discovery_get_gfx_info()
396 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->gc_num_max_gs_thds); in amdgpu_discovery_get_gfx_info()
397 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->gc_gs_table_depth); in amdgpu_discovery_get_gfx_info()
398 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->gc_gsprim_buff_depth); in amdgpu_discovery_get_gfx_info()
399 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->gc_double_offchip_lds_buffer); in amdgpu_discovery_get_gfx_info()
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| D | amdgpu_kms.c | 243 fw_info->ver = adev->gfx.me_fw_version; in amdgpu_firmware_info()
244 fw_info->feature = adev->gfx.me_feature_version; in amdgpu_firmware_info()
247 fw_info->ver = adev->gfx.pfp_fw_version; in amdgpu_firmware_info()
248 fw_info->feature = adev->gfx.pfp_feature_version; in amdgpu_firmware_info()
251 fw_info->ver = adev->gfx.ce_fw_version; in amdgpu_firmware_info()
252 fw_info->feature = adev->gfx.ce_feature_version; in amdgpu_firmware_info()
255 fw_info->ver = adev->gfx.rlc_fw_version; in amdgpu_firmware_info()
256 fw_info->feature = adev->gfx.rlc_feature_version; in amdgpu_firmware_info()
259 fw_info->ver = adev->gfx.rlc_srlc_fw_version; in amdgpu_firmware_info()
260 fw_info->feature = adev->gfx.rlc_srlc_feature_version; in amdgpu_firmware_info()
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| D | amdgpu_gfx.h | 28 * GFX stuff
34 /* GFX current status */
118 * GFX configurations
176 /* gfx configure feature */
301 /* gfx status */
312 /* gfx off */
315 … gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: ad…
326 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
327 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se…
328 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((a…
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| D | amdgpu_ucode.c | 98 DRM_DEBUG("GFX\n"); in amdgpu_ucode_print_gfx_hdr()
110 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor); in amdgpu_ucode_print_gfx_hdr()
420 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version);
421 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version);
422 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version);
423 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version);
424 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version);
425 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version);
426 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
427 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);
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| /kernel/linux/linux-4.19/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v9_0.c | 41 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
300 adev->gfx.scratch.num_reg = 8; in gfx_v9_0_scratch_init()
301 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v9_0_scratch_init()
302 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v9_0_scratch_init()
449 release_firmware(adev->gfx.pfp_fw); in gfx_v9_0_free_microcode()
450 adev->gfx.pfp_fw = NULL; in gfx_v9_0_free_microcode()
451 release_firmware(adev->gfx.me_fw); in gfx_v9_0_free_microcode()
452 adev->gfx.me_fw = NULL; in gfx_v9_0_free_microcode()
453 release_firmware(adev->gfx.ce_fw); in gfx_v9_0_free_microcode()
454 adev->gfx.ce_fw = NULL; in gfx_v9_0_free_microcode()
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| D | amdgpu_gfx.c | 45 i = ffs(adev->gfx.scratch.free_mask); in amdgpu_gfx_scratch_get()
46 if (i != 0 && i <= adev->gfx.scratch.num_reg) { in amdgpu_gfx_scratch_get()
48 adev->gfx.scratch.free_mask &= ~(1u << i); in amdgpu_gfx_scratch_get()
49 *reg = adev->gfx.scratch.reg_base + i; in amdgpu_gfx_scratch_get()
65 adev->gfx.scratch.free_mask |= 1u << (reg - adev->gfx.scratch.reg_base); in amdgpu_gfx_scratch_free()
125 return adev->gfx.mec.num_mec > 1; in amdgpu_gfx_is_multipipe_capable()
135 queue = i % adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_compute_queue_acquire()
136 pipe = (i / adev->gfx.mec.num_queue_per_pipe) in amdgpu_gfx_compute_queue_acquire()
137 % adev->gfx.mec.num_pipe_per_mec; in amdgpu_gfx_compute_queue_acquire()
138 mec = (i / adev->gfx.mec.num_queue_per_pipe) in amdgpu_gfx_compute_queue_acquire()
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| D | gfx_v6_0.c | 339 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v6_0_init_microcode()
342 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v6_0_init_microcode()
345 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v6_0_init_microcode()
346 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
347 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
350 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v6_0_init_microcode()
353 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v6_0_init_microcode()
356 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v6_0_init_microcode()
357 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
358 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
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| D | gfx_v7_0.c | 929 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
932 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v7_0_init_microcode()
937 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
940 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v7_0_init_microcode()
945 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
948 err = amdgpu_ucode_validate(adev->gfx.ce_fw); in gfx_v7_0_init_microcode()
953 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
956 err = amdgpu_ucode_validate(adev->gfx.mec_fw); in gfx_v7_0_init_microcode()
962 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
965 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); in gfx_v7_0_init_microcode()
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| D | gfx_v8_0.c | 828 adev->gfx.scratch.num_reg = 8; in gfx_v8_0_scratch_init()
829 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; in gfx_v8_0_scratch_init()
830 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v8_0_scratch_init()
943 release_firmware(adev->gfx.pfp_fw); in gfx_v8_0_free_microcode()
944 adev->gfx.pfp_fw = NULL; in gfx_v8_0_free_microcode()
945 release_firmware(adev->gfx.me_fw); in gfx_v8_0_free_microcode()
946 adev->gfx.me_fw = NULL; in gfx_v8_0_free_microcode()
947 release_firmware(adev->gfx.ce_fw); in gfx_v8_0_free_microcode()
948 adev->gfx.ce_fw = NULL; in gfx_v8_0_free_microcode()
949 release_firmware(adev->gfx.rlc_fw); in gfx_v8_0_free_microcode()
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| D | amdgpu_gfx.h | 68 bit += mec * adev->gfx.mec.num_pipe_per_mec in amdgpu_gfx_queue_to_bit()
69 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_queue_to_bit()
70 bit += pipe * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_queue_to_bit()
79 *queue = bit % adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_bit_to_queue()
80 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_gfx_bit_to_queue()
81 % adev->gfx.mec.num_pipe_per_mec; in amdgpu_gfx_bit_to_queue()
82 *mec = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_gfx_bit_to_queue()
83 / adev->gfx.mec.num_pipe_per_mec; in amdgpu_gfx_bit_to_queue()
90 adev->gfx.mec.queue_bitmap); in amdgpu_gfx_is_mec_queue_enabled()
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| D | amdgpu_kms.c | 169 fw_info->ver = adev->gfx.me_fw_version; in amdgpu_firmware_info()
170 fw_info->feature = adev->gfx.me_feature_version; in amdgpu_firmware_info()
173 fw_info->ver = adev->gfx.pfp_fw_version; in amdgpu_firmware_info()
174 fw_info->feature = adev->gfx.pfp_feature_version; in amdgpu_firmware_info()
177 fw_info->ver = adev->gfx.ce_fw_version; in amdgpu_firmware_info()
178 fw_info->feature = adev->gfx.ce_feature_version; in amdgpu_firmware_info()
181 fw_info->ver = adev->gfx.rlc_fw_version; in amdgpu_firmware_info()
182 fw_info->feature = adev->gfx.rlc_feature_version; in amdgpu_firmware_info()
185 fw_info->ver = adev->gfx.rlc_srlc_fw_version; in amdgpu_firmware_info()
186 fw_info->feature = adev->gfx.rlc_srlc_feature_version; in amdgpu_firmware_info()
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| D | amdgpu_atomfirmware.c | 345 adev->gfx.config.max_shader_engines = gfx_info->v24.gc_num_se; in amdgpu_atomfirmware_get_gfx_info()
346 adev->gfx.config.max_cu_per_sh = gfx_info->v24.gc_num_cu_per_sh; in amdgpu_atomfirmware_get_gfx_info()
347 adev->gfx.config.max_sh_per_se = gfx_info->v24.gc_num_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
348 adev->gfx.config.max_backends_per_se = gfx_info->v24.gc_num_rb_per_se; in amdgpu_atomfirmware_get_gfx_info()
349 adev->gfx.config.max_texture_channel_caches = gfx_info->v24.gc_num_tccs; in amdgpu_atomfirmware_get_gfx_info()
350 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs); in amdgpu_atomfirmware_get_gfx_info()
351 adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds; in amdgpu_atomfirmware_get_gfx_info()
352 adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth; in amdgpu_atomfirmware_get_gfx_info()
353 adev->gfx.config.gs_prim_buffer_depth = in amdgpu_atomfirmware_get_gfx_info()
355 adev->gfx.config.double_offchip_lds_buf = in amdgpu_atomfirmware_get_gfx_info()
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| D | amdgpu_debugfs.c | 144 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_process_reg_op()
145 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) in amdgpu_debugfs_process_reg_op()
455 * amdgpu_debugfs_gca_config_read - Read from gfx config data
485 config[no_regs++] = adev->gfx.config.max_shader_engines; in amdgpu_debugfs_gca_config_read()
486 config[no_regs++] = adev->gfx.config.max_tile_pipes; in amdgpu_debugfs_gca_config_read()
487 config[no_regs++] = adev->gfx.config.max_cu_per_sh; in amdgpu_debugfs_gca_config_read()
488 config[no_regs++] = adev->gfx.config.max_sh_per_se; in amdgpu_debugfs_gca_config_read()
489 config[no_regs++] = adev->gfx.config.max_backends_per_se; in amdgpu_debugfs_gca_config_read()
490 config[no_regs++] = adev->gfx.config.max_texture_channel_caches; in amdgpu_debugfs_gca_config_read()
491 config[no_regs++] = adev->gfx.config.max_gprs; in amdgpu_debugfs_gca_config_read()
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| D | amdgpu_amdkfd.c | 154 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, in amdgpu_amdkfd_device_init()
155 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, in amdgpu_amdkfd_device_init()
165 adev->gfx.mec.queue_bitmap, in amdgpu_amdkfd_device_init()
169 if (adev->gfx.kiq.ring.ready) in amdgpu_amdkfd_device_init()
171 adev->gfx.kiq.ring.me - 1, in amdgpu_amdkfd_device_init()
172 adev->gfx.kiq.ring.pipe, in amdgpu_amdkfd_device_init()
173 adev->gfx.kiq.ring.queue), in amdgpu_amdkfd_device_init()
179 * adev->gfx.mec.num_pipe_per_mec in amdgpu_amdkfd_device_init()
180 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_amdkfd_device_init()
392 if (adev->gfx.funcs->get_gpu_clock_counter) in get_gpu_clock_counter()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/gpu/ |
| D | aspeed-gfx.txt | 1 Device tree configuration for the GFX display device on the ASPEED SoCs
6 + aspeed,ast2500-gfx
7 + aspeed,ast2400-gfx
11 - reg: Physical base address and length of the GFX registers
13 - interrupts: interrupt number for the GFX device
17 - resets: reset line that must be released to use the GFX device
26 gfx: display@1e6e6000 {
27 compatible = "aspeed,ast2500-gfx", "syscon";
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mfd/ |
| D | aspeed-gfx.txt | 1 * Device tree bindings for Aspeed SoC Display Controller (GFX)
8 - compatible: "aspeed,ast2500-gfx", "syscon"
9 - reg: contains offset/length value of the GFX memory
14 gfx: display@1e6e6000 {
15 compatible = "aspeed,ast2500-gfx", "syscon";
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/mfd/ |
| D | aspeed-gfx.txt | 1 * Device tree bindings for Aspeed SoC Display Controller (GFX)
8 - compatible: "aspeed,ast2500-gfx", "syscon"
9 - reg: contains offset/length value of the GFX memory
14 gfx: display@1e6e6000 {
15 compatible = "aspeed,ast2500-gfx", "syscon";
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| /kernel/linux/linux-4.19/drivers/gpu/drm/amd/display/include/ |
| D | dal_asic_id.h | 46 /* KV1 with Spectre GFX core, 8-8-1-2 (CU-Pix-Primitive-RB) */
49 /* KV2 with Spooky GFX core, including downgraded from Spectre core,
53 /* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
56 /* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
59 /* BV with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
62 /* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
65 /* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
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