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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/interrupt-controller/
Darm,gic-v3.txt5 Software Generated Interrupts (SGI), and Locality-specific Peripheral
10 - compatible : should at least contain "arm,gic-v3".
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells : Specifies the number of cells needed to encode an
21 SPI interrupts are in the range [0-987]. PPI interrupts are in the
22 range [0-15].
31 pointed must be a subnode of the "ppi-partitions" subnode. For
33 this cell must be zero. See the "ppi-partitions" node description
39 - reg : Specifies base physical address(s) and size of the GIC
41 - GIC Distributor interface (GICD)
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
26 - qcom,msm8996-gic-v3
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/kernel/linux/linux-4.19/drivers/irqchip/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_IRQCHIP) += irqchip.o
4 obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o
5 obj-$(CONFIG_ATH79) += irq-ath79-cpu.o
6 obj-$(CONFIG_ATH79) += irq-ath79-misc.o
7 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
8 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
9 obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
10 obj-$(CONFIG_FARADAY_FTINTC010) += irq-ftintc010.o
11 obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o
[all …]
Dirq-gic-v3-its-fsl-mc-msi.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
19 .name = "ITS-fMSI",
34 return -EINVAL; in its_fsl_mc_msi_prepare()
37 if (!(mc_bus_dev->flags & FSL_MC_IS_DPRC)) in its_fsl_mc_msi_prepare()
38 return -EINVAL; in its_fsl_mc_msi_prepare()
41 * Set the device Id to be passed to the GIC-ITS: in its_fsl_mc_msi_prepare()
46 info->scratchpad[0].ul = mc_bus_dev->icid; in its_fsl_mc_msi_prepare()
47 msi_info = msi_get_domain_info(msi_domain->parent); in its_fsl_mc_msi_prepare()
51 return msi_info->ops->msi_prepare(msi_domain->parent, dev, nvec, info); in its_fsl_mc_msi_prepare()
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/kernel/linux/linux-5.10/drivers/irqchip/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_IRQCHIP) += irqchip.o
4 obj-$(CONFIG_AL_FIC) += irq-al-fic.o
5 obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o
6 obj-$(CONFIG_ATH79) += irq-ath79-cpu.o
7 obj-$(CONFIG_ATH79) += irq-ath79-misc.o
8 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
9 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
10 obj-$(CONFIG_ARCH_ACTIONS) += irq-owl-sirq.o
11 obj-$(CONFIG_DAVINCI_AINTC) += irq-davinci-aintc.o
[all …]
Dirq-gic-v3-its-fsl-mc-msi.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
21 .name = "ITS-fMSI",
35 out_id = of_node ? of_msi_map_id(&mc_dev->dev, of_node, mc_dev->icid) : in fsl_mc_msi_domain_get_msi_id()
36 iort_msi_map_id(&mc_dev->dev, mc_dev->icid); in fsl_mc_msi_domain_get_msi_id()
49 return -EINVAL; in its_fsl_mc_msi_prepare()
52 if (!(mc_bus_dev->flags & FSL_MC_IS_DPRC)) in its_fsl_mc_msi_prepare()
53 return -EINVAL; in its_fsl_mc_msi_prepare()
56 * Set the device Id to be passed to the GIC-ITS: in its_fsl_mc_msi_prepare()
61 info->scratchpad[0].ul = fsl_mc_msi_domain_get_msi_id(msi_domain, in its_fsl_mc_msi_prepare()
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/kernel/linux/linux-4.19/arch/arm64/boot/dts/arm/
Dfoundation-v8-gicv3.dtsi8 gic: interrupt-controller@2f000000 { label
9 compatible = "arm,gic-v3";
10 #interrupt-cells = <3>;
11 #address-cells = <2>;
12 #size-cells = <2>;
14 interrupt-controller;
22 its: its@2f020000 { label
23 compatible = "arm,gic-v3-its";
24 msi-controller;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/misc/
Dfsl,qoriq-mc.txt3 The Freescale Management Complex (fsl-mc) is a hardware resource
5 network-oriented packet processing applications. After the fsl-mc
12 For an overview of the DPAA2 architecture and fsl-mc bus see:
16 same hardware "isolation context" and a 10-bit value called an ICID
21 between ICIDs and IOMMUs, so an iommu-map property is used to define
28 For arm-smmu binding, see:
32 The msi-map property is used to associate the devices with both the ITS
36 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
38 For GICv3 and GIC ITS bindings, see:
39 Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml.
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/arm/
Dfoundation-v8-gicv3.dtsi8 gic: interrupt-controller@2f000000 { label
9 compatible = "arm,gic-v3";
10 #interrupt-cells = <3>;
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-controller;
22 its: msi-controller@2f020000 { label
23 compatible = "arm,gic-v3-its";
24 msi-controller;
25 #msi-cells = <1>;
Dfvp-base-revc.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
18 #include "rtsm_ve-motherboard-rs2.dtsi"
22 compatible = "arm,fvp-base-revc", "arm,vexpress";
23 interrupt-parent = <&gic>;
24 #address-cells = <2>;
25 #size-cells = <2>;
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/kernel/linux/linux-4.19/arch/arm64/boot/dts/ti/
Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
9 gic500: interrupt-controller@1800000 {
10 compatible = "arm,gic-v3";
11 #address-cells = <2>;
12 #size-cells = <2>;
14 #interrupt-cells = <3>;
15 interrupt-controller;
24 gic_its: gic-its@1820000 {
25 compatible = "arm,gic-v3-its";
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/cavium/
Dthunder2-99xx.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (c) 2013-2016 Broadcom
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc";
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
21 #address-cells = <0x2>;
22 #size-cells = <0x0>;
28 enable-method = "psci";
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/kernel/linux/linux-4.19/arch/arm64/boot/dts/cavium/
Dthunder2-99xx.dtsi5 * Copyright (c) 2013-2016 Broadcom
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
25 #address-cells = <0x2>;
26 #size-cells = <0x0>;
32 enable-method = "psci";
39 enable-method = "psci";
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/hisilicon/
Dhip05.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip05-d02";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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/kernel/linux/linux-4.19/arch/arm64/boot/dts/hisilicon/
Dhip05.dtsi12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 compatible = "hisilicon,hip05-d02";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 compatible = "arm,psci-0.2";
26 #address-cells = <1>;
27 #size-cells = <0>;
29 cpu-map {
90 compatible = "arm,cortex-a57", "arm,armv8";
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/marvell/
Darmada-ap810-ap0.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 /dts-v1/;
14 compatible = "marvell,armada-ap810";
15 #address-cells = <2>;
16 #size-cells = <2>;
24 compatible = "arm,psci-0.2";
28 ap810-ap0 {
29 #address-cells = <2>;
30 #size-cells = <2>;
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/kernel/linux/linux-4.19/arch/arm64/boot/dts/marvell/
Darmada-ap810-ap0.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 /dts-v1/;
14 compatible = "marvell,armada-ap810";
15 #address-cells = <2>;
16 #size-cells = <2>;
24 compatible = "arm,psci-0.2";
28 ap810-ap0 {
29 #address-cells = <2>;
30 #size-cells = <2>;
[all …]
/kernel/linux/linux-4.19/Documentation/virtual/kvm/devices/
Darm-vgic.txt9 controller, requiring emulated user-space devices to inject interrupts to the
14 device and guest ITS devices, see arm-vgic-v3.txt. It is not possible to
21 KVM_VGIC_V2_ADDR_TYPE_DIST (rw, 64-bit)
22 Base address in the guest physical address space of the GIC distributor
26 KVM_VGIC_V2_ADDR_TYPE_CPU (rw, 64-bit)
27 Base address in the guest physical address space of the GIC virtual cpu
31 -E2BIG: Address outside of addressable IPA range
32 -EINVAL: Incorrectly aligned address
33 -EEXIST: Address already configured
34 -ENXIO: The group or attribute is unknown/unsupported for this device
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/iommu/
Darm,smmu-v3.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
15 revisions, replacing the MMIO register interface with in-memory command
21 pattern: "^iommu@[0-9a-f]*"
23 const: arm,smmu-v3
32 interrupt-names:
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/freescale/
Dfsl-ls1088a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
24 #address-cells = <1>;
25 #size-cells = <0>;
27 /* We have 2 clusters having 4 Cortex-A53 cores each */
[all …]
Dfsl-ls208xa.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 /* DRAM space - 1, size : 2 GB DRAM */
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/amazon/
Dalpine-v3.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2020, Amazon.com, Inc. or its affiliates. All Rights Reserved
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 model = "Amazon's Annapurna Labs Alpine v3";
12 compatible = "amazon,al-alpine-v3";
14 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
[all …]
/kernel/linux/linux-5.10/include/kvm/
Darm_vgic.h1 /* SPDX-License-Identifier: GPL-2.0-only */
18 #include <linux/irqchip/arm-gic-v4.h>
26 #define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1)
30 #define KVM_IRQCHIP_NUM_PINS (1020 - 32)
41 /* same for all guests, as depending only on the _host's_ GIC model */
43 /* type of the host GIC */
75 /* GIC system register CPU interface */
85 #define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr)
105 * affinity reg (v3).
130 * Callback function pointer to in-kernel devices that can tell us the
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/kernel/linux/linux-4.19/include/kvm/
Darm_vgic.h29 #include <linux/irqchip/arm-gic-v4.h>
37 #define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1)
41 #define KVM_IRQCHIP_NUM_PINS (1020 - 32)
52 /* same for all guests, as depending only on the _host's_ GIC model */
54 /* type of the host GIC */
85 /* GIC system register CPU interface */
95 #define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr)
115 * affinity reg (v3).
140 * Callback function pointer to in-kernel devices that can tell us the
141 * state of the input level of mapped level-triggered IRQ faster than
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/broadcom/stingray/
Dstingray.dtsi4 * Copyright(c) 2015-2017 Broadcom. All rights reserved.
16 * * Neither the name of Broadcom nor the names of its
33 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 interrupt-parent = <&gic>;
38 #address-cells = <2>;
39 #size-cells = <2>;
42 #address-cells = <2>;
43 #size-cells = <0>;
47 compatible = "arm,cortex-a72", "arm,armv8";
49 enable-method = "psci";
[all …]

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