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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
26 - qcom,msm8996-gic-v3
[all …]
Dal,alpine-msix.txt3 See arm,gic-v3.txt for SPI and MSI definitions.
7 - compatible: should be "al,alpine-msix"
8 - reg: physical base address and size of the registers
9 - interrupt-controller: identifies the node as an interrupt controller
10 - msi-controller: identifies the node as an PCI Message Signaled Interrupt
12 - al,msi-base-spi: SPI base of the MSI frame
13 - al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0
18 compatible = "al,alpine-msix";
20 interrupt-parent = <&gic>;
21 interrupt-controller;
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/interrupt-controller/
Darm,gic-v3.txt5 Software Generated Interrupts (SGI), and Locality-specific Peripheral
10 - compatible : should at least contain "arm,gic-v3".
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells : Specifies the number of cells needed to encode an
21 SPI interrupts are in the range [0-987]. PPI interrupts are in the
22 range [0-15].
31 pointed must be a subnode of the "ppi-partitions" subnode. For
33 this cell must be zero. See the "ppi-partitions" node description
39 - reg : Specifies base physical address(s) and size of the GIC
41 - GIC Distributor interface (GICD)
[all …]
Dal,alpine-msix.txt3 See arm,gic-v3.txt for SPI and MSI definitions.
7 - compatible: should be "al,alpine-msix"
8 - reg: physical base address and size of the registers
9 - interrupt-controller: identifies the node as an interrupt controller
10 - msi-controller: identifies the node as an PCI Message Signaled Interrupt
12 - al,msi-base-spi: SPI base of the MSI frame
13 - al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0
18 compatible = "al,alpine-msix";
20 interrupt-parent = <&gic>;
21 interrupt-controller;
[all …]
/kernel/linux/linux-4.19/drivers/irqchip/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_IRQCHIP) += irqchip.o
4 obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o
5 obj-$(CONFIG_ATH79) += irq-ath79-cpu.o
6 obj-$(CONFIG_ATH79) += irq-ath79-misc.o
7 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
8 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
9 obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
10 obj-$(CONFIG_FARADAY_FTINTC010) += irq-ftintc010.o
11 obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o
[all …]
/kernel/linux/linux-5.10/drivers/irqchip/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_IRQCHIP) += irqchip.o
4 obj-$(CONFIG_AL_FIC) += irq-al-fic.o
5 obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o
6 obj-$(CONFIG_ATH79) += irq-ath79-cpu.o
7 obj-$(CONFIG_ATH79) += irq-ath79-misc.o
8 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
9 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
10 obj-$(CONFIG_ARCH_ACTIONS) += irq-owl-sirq.o
11 obj-$(CONFIG_DAVINCI_AINTC) += irq-davinci-aintc.o
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/arm/
Dfvp-base-revc.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
18 #include "rtsm_ve-motherboard-rs2.dtsi"
22 compatible = "arm,fvp-base-revc", "arm,vexpress";
23 interrupt-parent = <&gic>;
24 #address-cells = <2>;
25 #size-cells = <2>;
[all …]
Dfoundation-v8-gicv3.dtsi8 gic: interrupt-controller@2f000000 { label
9 compatible = "arm,gic-v3";
10 #interrupt-cells = <3>;
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-controller;
22 its: msi-controller@2f020000 {
23 compatible = "arm,gic-v3-its";
24 msi-controller;
25 #msi-cells = <1>;
/kernel/linux/linux-4.19/arch/arm64/boot/dts/arm/
Dfoundation-v8-gicv3.dtsi8 gic: interrupt-controller@2f000000 { label
9 compatible = "arm,gic-v3";
10 #interrupt-cells = <3>;
11 #address-cells = <2>;
12 #size-cells = <2>;
14 interrupt-controller;
23 compatible = "arm,gic-v3-its";
24 msi-controller;
/kernel/linux/linux-4.19/arch/arm64/boot/dts/ti/
Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
9 gic500: interrupt-controller@1800000 {
10 compatible = "arm,gic-v3";
11 #address-cells = <2>;
12 #size-cells = <2>;
14 #interrupt-cells = <3>;
15 interrupt-controller;
24 gic_its: gic-its@1820000 {
25 compatible = "arm,gic-v3-its";
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/hisilicon/
Dhip05.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip05-d02";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/hisilicon/
Dhip05.dtsi12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 compatible = "hisilicon,hip05-d02";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 compatible = "arm,psci-0.2";
26 #address-cells = <1>;
27 #size-cells = <0>;
29 cpu-map {
90 compatible = "arm,cortex-a57", "arm,armv8";
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/cavium/
Dthunder2-99xx.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (c) 2013-2016 Broadcom
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc";
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
21 #address-cells = <0x2>;
22 #size-cells = <0x0>;
28 enable-method = "psci";
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/misc/
Dfsl,qoriq-mc.txt3 The Freescale Management Complex (fsl-mc) is a hardware resource
5 network-oriented packet processing applications. After the fsl-mc
12 For an overview of the DPAA2 architecture and fsl-mc bus see:
16 same hardware "isolation context" and a 10-bit value called an ICID
21 between ICIDs and IOMMUs, so an iommu-map property is used to define
28 For arm-smmu binding, see:
32 The msi-map property is used to associate the devices with both the ITS
36 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
38 For GICv3 and GIC ITS bindings, see:
39 Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml.
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/cavium/
Dthunder2-99xx.dtsi5 * Copyright (c) 2013-2016 Broadcom
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
25 #address-cells = <0x2>;
26 #size-cells = <0x0>;
32 enable-method = "psci";
39 enable-method = "psci";
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/marvell/
Darmada-ap810-ap0.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 /dts-v1/;
14 compatible = "marvell,armada-ap810";
15 #address-cells = <2>;
16 #size-cells = <2>;
24 compatible = "arm,psci-0.2";
28 ap810-ap0 {
29 #address-cells = <2>;
30 #size-cells = <2>;
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/marvell/
Darmada-ap810-ap0.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 /dts-v1/;
14 compatible = "marvell,armada-ap810";
15 #address-cells = <2>;
16 #size-cells = <2>;
24 compatible = "arm,psci-0.2";
28 ap810-ap0 {
29 #address-cells = <2>;
30 #size-cells = <2>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/amazon/
Dalpine-v3.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 model = "Amazon's Annapurna Labs Alpine v3";
12 compatible = "amazon,al-alpine-v3";
14 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/renesas/
Dr8a779a0.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car V3U (R8A779A0) SoC
8 #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a779a0-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a76";
[all …]
/kernel/linux/linux-4.19/Documentation/virtual/kvm/devices/
Dvcpu.txt6 kvm_device_attr as other devices, but targets VCPU-wide settings and controls.
16 Returns: -EBUSY: The PMU overflow interrupt is already set
17 -ENXIO: The overflow interrupt not set when attempting to get it
18 -ENODEV: PMUv3 not supported
19 -EINVAL: Invalid PMU overflow interrupt number supplied or
20 trying to set the IRQ number without using an in-kernel
23 A value describing the PMUv3 (Performance Monitor Unit v3) overflow interrupt
30 Returns: -ENODEV: PMUv3 not supported or GIC not initialized
31 -ENXIO: PMUv3 not properly configured or in-kernel irqchip not
33 -EBUSY: PMUv3 already initialized
[all …]
Darm-vgic.txt9 controller, requiring emulated user-space devices to inject interrupts to the
14 device and guest ITS devices, see arm-vgic-v3.txt. It is not possible to
21 KVM_VGIC_V2_ADDR_TYPE_DIST (rw, 64-bit)
22 Base address in the guest physical address space of the GIC distributor
26 KVM_VGIC_V2_ADDR_TYPE_CPU (rw, 64-bit)
27 Base address in the guest physical address space of the GIC virtual cpu
31 -E2BIG: Address outside of addressable IPA range
32 -EINVAL: Incorrectly aligned address
33 -EEXIST: Address already configured
34 -ENXIO: The group or attribute is unknown/unsupported for this device
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/intel/
Dkeembay-soc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a53";
23 enable-method = "psci";
27 compatible = "arm,cortex-a53";
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/
Dpcie-al.txt5 Documentation/devicetree/bindings/pci/designware-pcie.txt.
9 - compatible:
13 - "amazon,al-alpine-v2-pcie" for alpine_v2
14 - "amazon,al-alpine-v3-pcie" for alpine_v3
16 - reg:
18 Value type: <prop-encoded-array>
19 Definition: Register ranges as listed in the reg-names property
21 - reg-names:
25 - "config" PCIe ECAM space
26 - "controller" AL proprietary registers
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/iommu/
Darm,smmu-v3.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
15 revisions, replacing the MMIO register interface with in-memory command
21 pattern: "^iommu@[0-9a-f]*"
23 const: arm,smmu-v3
32 interrupt-names:
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/
Dspe-pmu.txt4 performance sample data using an in-memory trace buffer.
8 - compatible : should be one of:
9 "arm,statistical-profiling-extension-v1"
11 - interrupts : Exactly 1 PPI must be listed. For heterogeneous systems where
13 the arm,gic-v3 binding for details on describing a PPI partition.
17 spe-pmu {
18 compatible = "arm,statistical-profiling-extension-v1";

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