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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/hisilicon/controller/
Dsysctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/hisilicon/controller/sysctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wei Xu <xuwei5@hisilicon.com>
16 There are some variants of the Hisilicon system controller, such as HiP01,
19 offset. In addition, the HiP01 system controller has some specific control
20 registers for HIP01 SoC family, such as slave core boot.
23 Hisilicon system controller --> hisilicon,sysctrl
24 HiP01 system controller --> hisilicon,hip01-sysctrl
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/hisilicon/
Dhisilicon.txt2 ----------------------------------------------------
5 - compatible = "hisilicon,hi3660";
9 - compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
13 - compatible = "hisilicon,hi3798cv200";
17 - compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200";
21 - compatible = "hisilicon,hi3620-hi4511";
25 - compatible = "hisilicon,hi6220";
29 - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
31 HiP01 ca9x2 Board
33 - compatible = "hisilicon,hip01-ca9x2";
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dhip01.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Hisilicon Ltd. HiP01 SoC
12 interrupt-parent = <&gic>;
13 #address-cells = <1>;
14 #size-cells = <1>;
16 gic: interrupt-controller@1e001000 {
17 compatible = "arm,cortex-a9-gic";
18 #interrupt-cells = <3>;
19 #address-cells = <0>;
20 interrupt-controller;
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dhip01.dtsi2 * Hisilicon Ltd. HiP01 SoC
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
19 gic: interrupt-controller@1e001000 {
20 compatible = "arm,cortex-a9-gic";
21 #interrupt-cells = <3>;
22 #address-cells = <0>;
23 interrupt-controller;
28 compatible = "fixed-clock";
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-hisi/
Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Based on arch/arm/mach-vexpress/platsmp.c, Copyright (C) 2002 ARM Ltd.
28 writel_relaxed(__pa_symbol(jump_addr), ctrl_base + ((cpu - 1) << 2)); in hi3xxx_set_cpu_jump()
36 return readl_relaxed(ctrl_base + ((cpu - 1) << 2)); in hi3xxx_get_cpu_jump()
63 np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl"); in hi3xxx_smp_prepare_cpus()
65 pr_err("failed to find hisilicon,sysctrl node\n"); in hi3xxx_smp_prepare_cpus()
73 if (of_property_read_u32(np, "smp-offset", &offset) < 0) { in hi3xxx_smp_prepare_cpus()
74 pr_err("failed to find smp-offset property\n"); in hi3xxx_smp_prepare_cpus()
109 writel_relaxed(0xe51ff004, virt); /* ldr pc, [pc, #-4] */ in hix5hd2_set_scu_boot_addr()
159 node = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl"); in hip01_boot_secondary()
[all …]
Dhotplug.c1 // SPDX-License-Identifier: GPL-2.0-only
16 /* Sysctrl registers in Hi3620 SoC */
83 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), in set_cpu_hi3620()
100 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), in set_cpu_hi3620()
124 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), in set_cpu_hi3620()
136 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), in set_cpu_hi3620()
147 node = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl"); in hi3xxx_hotplug_init()
150 return -ENOENT; in hi3xxx_hotplug_init()
157 return -ENOMEM; in hi3xxx_hotplug_init()
229 np = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl"); in hip01_set_cpu()
[all …]
/kernel/linux/linux-4.19/arch/arm/mach-hisi/
Dplatsmp.c4 * Based on arch/arm/mach-vexpress/platsmp.c, Copyright (C) 2002 ARM Ltd.
31 writel_relaxed(__pa_symbol(jump_addr), ctrl_base + ((cpu - 1) << 2)); in hi3xxx_set_cpu_jump()
39 return readl_relaxed(ctrl_base + ((cpu - 1) << 2)); in hi3xxx_get_cpu_jump()
66 np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl"); in hi3xxx_smp_prepare_cpus()
68 pr_err("failed to find hisilicon,sysctrl node\n"); in hi3xxx_smp_prepare_cpus()
76 if (of_property_read_u32(np, "smp-offset", &offset) < 0) { in hi3xxx_smp_prepare_cpus()
77 pr_err("failed to find smp-offset property\n"); in hi3xxx_smp_prepare_cpus()
112 writel_relaxed(0xe51ff004, virt); /* ldr pc, [pc, #-4] */ in hix5hd2_set_scu_boot_addr()
162 node = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl"); in hip01_boot_secondary()
164 return -1; in hip01_boot_secondary()
[all …]
Dhotplug.c19 /* Sysctrl registers in Hi3620 SoC */
86 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), in set_cpu_hi3620()
103 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), in set_cpu_hi3620()
127 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), in set_cpu_hi3620()
139 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), in set_cpu_hi3620()
150 node = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl"); in hi3xxx_hotplug_init()
153 return -ENOENT; in hi3xxx_hotplug_init()
160 return -ENOMEM; in hi3xxx_hotplug_init()
232 np = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl"); in hip01_set_cpu()
261 * Turn off coherency and L1 D-cache in cpu_enter_lowpower()