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/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/knightslanding/
D	cache.json	59 "BriefDescription": "Counts the number of load micro-ops retired that hit in the L2", 135 …nts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded… 146 …nts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded… 157 …nts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded… 168 …nts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded… 201 …"Counts any Read request that accounts for responses from a snoop request hit with data forwarded… 212 …"Counts any Read request that accounts for responses from a snoop request hit with data forwarded… 223 …"Counts any Read request that accounts for responses from a snoop request hit with data forwarded… 234 …"Counts any Read request that accounts for responses from a snoop request hit with data forwarded… 267 …fetch code read requests that accounts for responses from a snoop request hit with data forwarded… [all …]
/kernel/linux/linux-4.19/tools/perf/pmu-events/arch/x86/knightslanding/
D	cache.json	59 "BriefDescription": "Counts the number of load micro-ops retired that hit in the L2", 135 …nts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded… 146 …nts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded… 157 …nts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded… 168 …nts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded… 201 …"Counts any Read request that accounts for responses from a snoop request hit with data forwarded… 212 …"Counts any Read request that accounts for responses from a snoop request hit with data forwarded… 223 …"Counts any Read request that accounts for responses from a snoop request hit with data forwarded… 234 …"Counts any Read request that accounts for responses from a snoop request hit with data forwarded… 267 …fetch code read requests that accounts for responses from a snoop request hit with data forwarded… [all …]
/kernel/linux/linux-4.19/tools/perf/pmu-events/arch/x86/haswell/
D	cache.json	66 "PublicDescription": "Demand data read requests that hit L2 cache.", 73 "BriefDescription": "Demand Data Read requests that hit L2 cache", 77 "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.", 83 "BriefDescription": "RFO requests that hit L2 cache", 87 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 97 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 103 "BriefDescription": "L2 prefetch requests that hit L2 cache", 170 "PublicDescription": "Not rejected writebacks that hit L2 cache.", 176 "BriefDescription": "Not rejected writebacks that hit L2 cache", 588 …"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due … [all …]
D	virtual-memory.json	62 …t counts load operations from a 4K page that miss the first DTLB level but hit the second and do n… 68 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", 72 …t counts load operations from a 2M page that miss the first DTLB level but hit the second and do n… 78 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", 88 …"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not … 161 … counts store operations from a 4K page that miss the first DTLB level but hit the second and do n… 167 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)", 171 … counts store operations from a 2M page that miss the first DTLB level but hit the second and do n… 177 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)", 181 …"PublicDescription": "Store operations that miss the first TLB level but hit the second and do not… [all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/haswell/
D	cache.json	66 …Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache", 73 "BriefDescription": "Demand Data Read requests that hit L2 cache", 77 "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.", 83 "BriefDescription": "RFO requests that hit L2 cache", 87 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 97 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 103 "BriefDescription": "L2 prefetch requests that hit L2 cache", 170 "PublicDescription": "Not rejected writebacks that hit L2 cache.", 176 "BriefDescription": "Not rejected writebacks that hit L2 cache", 588 …"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due … [all …]
D	virtual-memory.json	62 …t counts load operations from a 4K page that miss the first DTLB level but hit the second and do n… 68 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", 72 …t counts load operations from a 2M page that miss the first DTLB level but hit the second and do n… 78 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", 88 …"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not … 161 … counts store operations from a 4K page that miss the first DTLB level but hit the second and do n… 167 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)", 171 … counts store operations from a 2M page that miss the first DTLB level but hit the second and do n… 177 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)", 181 …"PublicDescription": "Store operations that miss the first TLB level but hit the second and do not… [all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/goldmont/
D	cache.json	158 "PublicDescription": "Counts load uops retired that hit the L1 data cache.", 164 "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)", 170 "PublicDescription": "Counts load uops retired that hit in the L2 cache.", 176 "BriefDescription": "Load uops retired that hit L2 (Precise event capable)", 218 …ess of requesting the data. When load Y requests the data, it will either hit the WCB, or the L1 … 224 "BriefDescription": "Loads retired that hit WCB (Precise event capable)", 230 …ive loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, … 254 …hip (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other proces… 262 …hip (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other proces… 267 …hip (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other proces… [all …]
/kernel/linux/linux-4.19/tools/perf/pmu-events/arch/x86/sandybridge/
D	cache.json	98 …"PublicDescription": "This event counts retired load uops that hit in the last-level (L3) cache wi… 114 …"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due … 124 …"BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed… 129 …"PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) an… 140 …"PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) an… 333 "BriefDescription": "Demand Data Read requests that hit L2 cache.", 342 "BriefDescription": "RFO requests that hit L2 cache.", 378 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache.", 405 "BriefDescription": "RFOs that hit cache lines in E state.", 414 "BriefDescription": "RFOs that hit cache lines in M state.", [all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/haswellx/
D	cache.json	68 "BriefDescription": "Demand Data Read requests that hit L2 cache", 72 …Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache", 79 "BriefDescription": "RFO requests that hit L2 cache", 82 "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.", 92 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 99 "BriefDescription": "L2 prefetch requests that hit L2 cache", 102 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 172 "BriefDescription": "Not rejected writebacks that hit L2 cache", 175 "PublicDescription": "Not rejected writebacks that hit L2 cache.", 582 …"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due … [all …]
D	virtual-memory.json	64 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", 67 …t counts load operations from a 4K page that miss the first DTLB level but hit the second and do n… 74 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", 77 …t counts load operations from a 2M page that miss the first DTLB level but hit the second and do n… 84 …"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not … 163 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)", 166 … counts store operations from a 4K page that miss the first DTLB level but hit the second and do n… 173 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)", 176 … counts store operations from a 2M page that miss the first DTLB level but hit the second and do n… 183 …"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not … [all …]
/kernel/linux/linux-4.19/tools/perf/pmu-events/arch/x86/haswellx/
D	cache.json	68 "BriefDescription": "Demand Data Read requests that hit L2 cache", 72 "PublicDescription": "Demand data read requests that hit L2 cache.", 79 "BriefDescription": "RFO requests that hit L2 cache", 82 "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.", 92 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 99 "BriefDescription": "L2 prefetch requests that hit L2 cache", 102 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 172 "BriefDescription": "Not rejected writebacks that hit L2 cache", 175 "PublicDescription": "Not rejected writebacks that hit L2 cache.", 583 …"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due … [all …]
D	virtual-memory.json	64 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", 67 …t counts load operations from a 4K page that miss the first DTLB level but hit the second and do n… 74 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", 77 …t counts load operations from a 2M page that miss the first DTLB level but hit the second and do n… 84 …"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not … 163 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)", 166 … counts store operations from a 4K page that miss the first DTLB level but hit the second and do n… 173 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)", 176 … counts store operations from a 2M page that miss the first DTLB level but hit the second and do n… 183 …"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not … [all …]
/kernel/linux/linux-4.19/tools/perf/pmu-events/arch/x86/skylakex/
D	cache.json	65 "BriefDescription": "Demand Data Read requests that hit L2 cache", 68 …"PublicDescription": "Counts the number of demand Data Read requests that hit L2 cache. Only non r… 75 "BriefDescription": "RFO requests that hit L2 cache", 78 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", 95 …": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache", 98 …ts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache.", 108 …quests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. O… 188 …hit at least once by demand. The valid outstanding interval is defined until the FB deallocation b… 489 …"PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 da… 556 …on": "Retired load instructions which data sources were load missed L1 but hit FB due to preceding… [all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/sandybridge/
D	cache.json	8 "BriefDescription": "Demand Data Read requests that hit L2 cache.", 26 "BriefDescription": "RFO requests that hit L2 cache.", 80 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache.", 116 "BriefDescription": "RFOs that hit cache lines in E state.", 125 "BriefDescription": "RFOs that hit cache lines in M state.", 504 …"PublicDescription": "This event counts retired load uops that hit in the last-level (L3) cache wi… 520 …"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due … 530 …"BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed… 535 …"PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) an… 546 …"PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) an… [all …]
/kernel/linux/linux-4.19/tools/perf/pmu-events/arch/x86/broadwell/
D	cache.json	59 …"PublicDescription": "This event counts the number of demand Data Read requests that hit L2 cache.… 65 "BriefDescription": "Demand Data Read requests that hit L2 cache", 74 "BriefDescription": "RFO requests that hit L2 cache.", 87 … event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefet… 93 "BriefDescription": "L2 prefetch requests that hit L2 cache", 97 …quests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. O… 155 "PublicDescription": "This event counts the number of WB requests that hit L2 cache.", 161 "BriefDescription": "Not rejected writebacks that hit L2 cache", 185 …hit at least once by demand. The valid outstanding interval is defined until the FB deallocation b… 518 …"BriefDescription": "Hit in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - … [all …]
/kernel/linux/linux-4.19/tools/perf/pmu-events/arch/x86/goldmont/
D	cache.json	151 "PublicDescription": "Counts load uops retired that hit the L1 data cache.", 157 "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)" 162 "PublicDescription": "Counts load uops retired that hit in the L2 cache.", 168 "BriefDescription": "Load uops retired that hit L2 (Precise event capable)" 206 …ess of requesting the data. When load Y requests the data, it will either hit the WCB, or the L1 … 212 "BriefDescription": "Loads retired that hit WCB (Precise event capable)" 217 …ive loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, … 253 …hip (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other proces… 261 …hip (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other proces… 266 …hip (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other proces… [all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/arm64/ampere/emag/
D	cache.json	162 "PublicDescription": "Page walk cache level-0 stage-1 hit", 165 "BriefDescription": "Page walk, L0 stage-1 hit" 168 "PublicDescription": "Page walk cache level-1 stage-1 hit", 171 "BriefDescription": "Page walk, L1 stage-1 hit" 174 "PublicDescription": "Page walk cache level-2 stage-1 hit", 177 "BriefDescription": "Page walk, L2 stage-1 hit" 180 "PublicDescription": "Page walk cache level-1 stage-2 hit", 183 "BriefDescription": "Page walk, L1 stage-2 hit" 186 "PublicDescription": "Page walk cache level-2 stage-2 hit", 189 "BriefDescription": "Page walk, L2 stage-2 hit"
/kernel/linux/linux-4.19/Documentation/device-mapper/
D	cache-policies.txt	11 The policy can return a simple HIT or MISS or issue a migration. 20 doesn't update states (eg, hit counts) for a block more than once 64 pointers. It avoids storing an explicit hit count for each block. It 74 based on their hit count (~ln(hit count)). This meant the bottom 79 smq does not maintain a hit count, instead it swaps hit entries with 86 The mq policy maintained a hit count for each cache block. For a 87 different block to get promoted to the cache its hit count has to 91 smq doesn't maintain hit counts, so a lot of this problem just goes
/kernel/linux/linux-4.19/tools/perf/pmu-events/arch/x86/broadwellx/
D	cache.json	61 "BriefDescription": "Demand Data Read requests that hit L2 cache", 64 …"PublicDescription": "This event counts the number of demand Data Read requests that hit L2 cache.… 71 "BriefDescription": "RFO requests that hit L2 cache.", 89 "BriefDescription": "L2 prefetch requests that hit L2 cache", 92 … event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefet… 102 …quests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. O… 157 "BriefDescription": "Not rejected writebacks that hit L2 cache", 160 "PublicDescription": "This event counts the number of WB requests that hit L2 cache.", 190 …hit at least once by demand. The valid outstanding interval is defined until the FB deallocation b… 512 …"BriefDescription": "Hit in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - … [all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/broadwellx/
D	cache.json	61 "BriefDescription": "Demand Data Read requests that hit L2 cache", 64 …ounts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache.", 71 "BriefDescription": "RFO requests that hit L2 cache.", 89 "BriefDescription": "L2 prefetch requests that hit L2 cache", 92 … event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefet… 102 …quests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. O… 157 "BriefDescription": "Not rejected writebacks that hit L2 cache", 160 "PublicDescription": "This event counts the number of WB requests that hit L2 cache.", 190 …hit at least once by demand. The valid outstanding interval is defined until the FB deallocation b… 561 …"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due … [all …]
/kernel/linux/linux-5.10/Documentation/admin-guide/device-mapper/
D	cache-policies.rst	12 The policy can return a simple HIT or MISS or issue a migration. 21 doesn't update states (eg, hit counts) for a block more than once 67 pointers. It avoids storing an explicit hit count for each block. It 79 based on their hit count (~ln(hit count)). This meant the bottom 84 smq does not maintain a hit count, instead it swaps hit entries with 91 The mq policy maintained a hit count for each cache block. For a 92 different block to get promoted to the cache its hit count has to 96 smq doesn't maintain hit counts, so a lot of this problem just goes
/kernel/linux/linux-4.19/tools/perf/pmu-events/arch/x86/goldmontplus/
D	cache.json	172 "PublicDescription": "Counts load uops retired that hit the L1 data cache.", 179 "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)" 184 "PublicDescription": "Counts load uops retired that hit in the L2 cache.", 191 "BriefDescription": "Load uops retired that hit L2 (Precise event capable)" 232 …ess of requesting the data. When load Y requests the data, it will either hit the WCB, or the L1 … 239 "BriefDescription": "Loads retired that hit WCB (Precise event capable)" 244 …ive loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, … 270 …"PublicDescription": "Counts demand cacheable data reads of full cache lines hit the L2 cache. Req… 280 … "BriefDescription": "Counts demand cacheable data reads of full cache lines hit the L2 cache.", 300 …nd cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other proces… [all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/goldmontplus/
D	cache.json	179 "PublicDescription": "Counts load uops retired that hit the L1 data cache.", 186 "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)", 192 "PublicDescription": "Counts load uops retired that hit in the L2 cache.", 199 "BriefDescription": "Load uops retired that hit L2 (Precise event capable)", 244 …ess of requesting the data. When load Y requests the data, it will either hit the WCB, or the L1 … 251 "BriefDescription": "Loads retired that hit WCB (Precise event capable)", 257 …ive loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, … 284 …"PublicDescription": "Counts demand cacheable data reads of full cache lines hit the L2 cache. Req… 294 … "BriefDescription": "Counts demand cacheable data reads of full cache lines hit the L2 cache.", 314 …nd cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other proces… [all …]
/kernel/linux/linux-4.19/tools/perf/pmu-events/arch/x86/ivytown/
D	cache.json	3 "PublicDescription": "Demand Data Read requests that hit L2 cache.", 9 "BriefDescription": "Demand Data Read requests that hit L2 cache", 23 "PublicDescription": "RFO requests that hit L2 cache.", 29 "BriefDescription": "RFO requests that hit L2 cache", 53 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 83 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 89 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache", 123 "PublicDescription": "RFOs that hit cache lines in M state.", 129 "BriefDescription": "RFOs that hit cache lines in M state", 546 …"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due … [all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/ivytown/
D	cache.json	3 "PublicDescription": "Demand Data Read requests that hit L2 cache.", 9 "BriefDescription": "Demand Data Read requests that hit L2 cache", 23 "PublicDescription": "RFO requests that hit L2 cache.", 29 "BriefDescription": "RFO requests that hit L2 cache", 53 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 83 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 89 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache", 123 "PublicDescription": "RFOs that hit cache lines in M state.", 129 "BriefDescription": "RFOs that hit cache lines in M state", 546 …"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due … [all …]

12 3 4 5 6 7 8 9 10 >>...89