| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/phy/ |
| D | qcom,usb-hsic-phy.txt | 1 Qualcomm's USB HSIC PHY
5 - compatible:
8 Definition: Should contain "qcom,usb-hsic-phy" and more specifically one of the
11 "qcom,usb-hsic-phy-mdm9615"
12 "qcom,usb-hsic-phy-msm8974"
14 - #phy-cells:
19 - clocks:
21 Value type: <prop-encoded-array>
22 Definition: Should contain clock specifier for phy, calibration and
25 - clock-names:
[all …]
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| D | nvidia,tegra124-xusb-padctl.txt | 11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
29 abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
34 --------------------
[all …]
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| D | sun9i-usb-phy.txt | 1 Allwinner sun9i USB PHY
2 -----------------------
5 - compatible : should be one of
6 * allwinner,sun9i-a80-usb-phy
7 - reg : a list of offset + length pairs
8 - #phy-cells : from the generic phy bindings, must be 0
9 - phy_type : "hsic" for HSIC usage;
11 - clocks : phandle + clock specifier for the phy clocks
12 - clock-names : depending on the "phy_type" property,
13 * "phy" for normal USB
[all …]
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| D | pxa1928-usb-phy.txt | 1 * Marvell PXA1928 USB and HSIC PHYs
4 - compatible: "marvell,pxa1928-usb-phy" or "marvell,pxa1928-hsic-phy"
5 - reg: base address and length of the registers
6 - clocks - A single clock. From common clock binding.
7 - #phys-cells: should be 0. From commmon phy binding.
8 - resets: reference to the reset controller
12 usbphy: phy@7000 {
13 compatible = "marvell,pxa1928-usb-phy";
16 #phy-cells = <0>;
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | qcom,usb-hsic-phy.txt | 1 Qualcomm's USB HSIC PHY
5 - compatible:
8 Definition: Should contain "qcom,usb-hsic-phy" and more specifically one of the
11 "qcom,usb-hsic-phy-mdm9615"
12 "qcom,usb-hsic-phy-msm8974"
14 - #phy-cells:
19 - clocks:
21 Value type: <prop-encoded-array>
22 Definition: Should contain clock specifier for phy, calibration and
25 - clock-names:
[all …]
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| D | allwinner,sun9i-a80-usb-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun9i-a80-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A80 USB PHY Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun9i-a80-usb-phy
25 - description: Main PHY Clock
[all …]
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| D | nvidia,tegra124-xusb-padctl.txt | 11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
29 abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
34 --------------------
[all …]
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| D | marvell,mmp3-hsic-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0-or-later
4 ---
5 $id: "http://devicetree.org/schemas/phy/marvell,mmp3-hsic-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Marvell MMP3 HSIC PHY
11 - Lubomir Rintel <lkundrak@v3.sk>
15 const: marvell,mmp3-hsic-phy
21 reset-gpios:
25 "#phy-cells":
29 - compatible
[all …]
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| D | pxa1928-usb-phy.txt | 1 * Marvell PXA1928 USB and HSIC PHYs
4 - compatible: "marvell,pxa1928-usb-phy" or "marvell,pxa1928-hsic-phy"
5 - reg: base address and length of the registers
6 - clocks - A single clock. From common clock binding.
7 - #phys-cells: should be 0. From commmon phy binding.
8 - resets: reference to the reset controller
12 usbphy: phy@7000 {
13 compatible = "marvell,pxa1928-usb-phy";
16 #phy-cells = <0>;
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| /kernel/linux/linux-5.10/drivers/phy/marvell/ |
| D | phy-pxa-28nm-hsic.c | 1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <linux/phy/phy.h>
42 struct phy *phy; member
56 static int mv_hsic_phy_init(struct phy *phy) in mv_hsic_phy_init() argument
58 struct mv_hsic_phy *mv_phy = phy_get_drvdata(phy); in mv_hsic_phy_init()
59 struct platform_device *pdev = mv_phy->pdev; in mv_hsic_phy_init()
60 void __iomem *base = mv_phy->base; in mv_hsic_phy_init()
63 clk_prepare_enable(mv_phy->clk); in mv_hsic_phy_init()
76 /* Make sure PHY PLL is locked */ in mv_hsic_phy_init()
80 dev_err(&pdev->dev, "HSIC PHY PLL not locked after 100mS."); in mv_hsic_phy_init()
[all …]
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| /kernel/linux/linux-4.19/drivers/phy/marvell/ |
| D | phy-pxa-28nm-hsic.c | 28 #include <linux/phy/phy.h>
50 struct phy *phy; member
67 static int mv_hsic_phy_init(struct phy *phy) in mv_hsic_phy_init() argument
69 struct mv_hsic_phy *mv_phy = phy_get_drvdata(phy); in mv_hsic_phy_init()
70 struct platform_device *pdev = mv_phy->pdev; in mv_hsic_phy_init()
71 void __iomem *base = mv_phy->base; in mv_hsic_phy_init()
73 clk_prepare_enable(mv_phy->clk); in mv_hsic_phy_init()
86 /* Make sure PHY PLL is locked */ in mv_hsic_phy_init()
89 dev_err(&pdev->dev, "HSIC PHY PLL not locked after 100mS."); in mv_hsic_phy_init()
90 clk_disable_unprepare(mv_phy->clk); in mv_hsic_phy_init()
[all …]
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| /kernel/linux/linux-5.10/drivers/phy/tegra/ |
| D | xusb-tegra124.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/phy/phy.h>
229 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_enable()
231 if (padctl->enable++ > 0) in tegra124_xusb_padctl_enable()
251 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_enable()
259 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_disable()
261 if (WARN_ON(padctl->enable == 0)) in tegra124_xusb_padctl_disable()
264 if (--padctl->enable > 0) in tegra124_xusb_padctl_disable()
284 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_disable()
297 return -ENODEV; in tegra124_usb3_save_context()
[all …]
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| D | xusb-tegra210.c | 1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/phy/phy.h>
25 ((x) ? (11 + ((x) - 1) * 6) : 0)
259 /* must be called under padctl->lock */
262 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie); in tegra210_pex_uphy_enable()
267 if (pcie->enable > 0) { in tegra210_pex_uphy_enable()
268 pcie->enable++; in tegra210_pex_uphy_enable()
272 err = clk_prepare_enable(pcie->pll); in tegra210_pex_uphy_enable()
276 err = reset_control_deassert(pcie->rst); in tegra210_pex_uphy_enable()
355 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
[all …]
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| D | xusb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
12 #include <linux/phy/phy.h>
13 #include <linux/phy/tegra/xusb.h>
24 static struct phy *tegra_xusb_pad_of_xlate(struct device *dev, in tegra_xusb_pad_of_xlate()
28 struct phy *phy = NULL; in tegra_xusb_pad_of_xlate() local
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
[all …]
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| /kernel/linux/linux-4.19/drivers/phy/tegra/ |
| D | xusb-tegra124.c | 19 #include <linux/phy/phy.h>
237 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_enable()
239 if (padctl->enable++ > 0) in tegra124_xusb_padctl_enable()
259 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_enable()
267 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_disable()
269 if (WARN_ON(padctl->enable == 0)) in tegra124_xusb_padctl_disable()
272 if (--padctl->enable > 0) in tegra124_xusb_padctl_disable()
292 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_disable()
305 return -ENODEV; in tegra124_usb3_save_context()
307 port->context_saved = true; in tegra124_usb3_save_context()
[all …]
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| D | xusb-tegra210.c | 22 #include <linux/phy/phy.h>
33 ((x) ? (11 + ((x) - 1) * 6) : 0)
251 /* must be called under padctl->lock */
254 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie); in tegra210_pex_uphy_enable()
259 if (pcie->enable > 0) { in tegra210_pex_uphy_enable()
260 pcie->enable++; in tegra210_pex_uphy_enable()
264 err = clk_prepare_enable(pcie->pll); in tegra210_pex_uphy_enable()
268 err = reset_control_deassert(pcie->rst); in tegra210_pex_uphy_enable()
347 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
366 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
[all …]
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| D | xusb.c | 2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
20 #include <linux/phy/phy.h>
21 #include <linux/phy/tegra/xusb.h>
32 static struct phy *tegra_xusb_pad_of_xlate(struct device *dev, in tegra_xusb_pad_of_xlate()
36 struct phy *phy = NULL; in tegra_xusb_pad_of_xlate() local
39 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
40 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
42 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
43 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
46 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate()
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/mfd/ |
| D | omap-usb-host.txt | 5 - compatible: should be "ti,usbhs-host"
6 - reg: should contain one register range i.e. start and length
7 - ti,hwmods: must contain "usb_host_hs"
11 - num-ports: number of USB ports. Usually this is automatically detected
15 - portN-mode: String specifying the port mode for port N, where N can be
18 "ehci-phy",
19 "ehci-tll",
20 "ehci-hsic",
21 "ohci-phy-6pin-datse0",
22 "ohci-phy-6pin-dpdm",
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mfd/ |
| D | omap-usb-host.txt | 5 - compatible: should be "ti,usbhs-host"
6 - reg: should contain one register range i.e. start and length
7 - ti,hwmods: must contain "usb_host_hs"
11 - num-ports: number of USB ports. Usually this is automatically detected
15 - portN-mode: String specifying the port mode for port N, where N can be
18 "ehci-phy",
19 "ehci-tll",
20 "ehci-hsic",
21 "ohci-phy-6pin-datse0",
22 "ohci-phy-6pin-dpdm",
[all …]
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| /kernel/linux/linux-5.10/drivers/phy/samsung/ |
| D | phy-exynos5250-usb2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 5250 support
11 #include <linux/phy/phy.h>
13 #include "phy-samsung-usb2.h"
15 /* Exynos USB PHY registers */
140 * can be written to the phy register.
169 return -EINVAL; in exynos5250_rate_to_clk()
177 struct samsung_usb2_phy_driver *drv = inst->drv; in exynos5250_isol()
181 switch (inst->cfg->id) { in exynos5250_isol()
194 regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask); in exynos5250_isol()
[all …]
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| /kernel/linux/linux-4.19/drivers/phy/samsung/ |
| D | phy-exynos5250-usb2.c | 2 * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 5250 support
14 #include <linux/phy/phy.h>
16 #include "phy-samsung-usb2.h"
18 /* Exynos USB PHY registers */
143 * can be written to the phy register.
172 return -EINVAL; in exynos5250_rate_to_clk()
180 struct samsung_usb2_phy_driver *drv = inst->drv; in exynos5250_isol()
184 switch (inst->cfg->id) { in exynos5250_isol()
197 regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask); in exynos5250_isol()
202 struct samsung_usb2_phy_driver *drv = inst->drv; in exynos5250_power_on()
[all …]
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| /kernel/linux/linux-5.10/drivers/phy/qualcomm/ |
| D | phy-qcom-usb-hsic.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/phy/phy.h>
10 #include <linux/pinctrl/pinctrl-state.h>
19 struct phy *phy; member
26 static int qcom_usb_hsic_phy_power_on(struct phy *phy) in qcom_usb_hsic_phy_power_on() argument
28 struct qcom_usb_hsic_phy *uphy = phy_get_drvdata(phy); in qcom_usb_hsic_phy_power_on()
29 struct ulpi *ulpi = uphy->ulpi; in qcom_usb_hsic_phy_power_on()
33 ret = clk_prepare_enable(uphy->phy_clk); in qcom_usb_hsic_phy_power_on()
37 ret = clk_prepare_enable(uphy->cal_clk); in qcom_usb_hsic_phy_power_on()
41 ret = clk_prepare_enable(uphy->cal_sleep_clk); in qcom_usb_hsic_phy_power_on()
[all …]
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| /kernel/linux/linux-4.19/drivers/phy/qualcomm/ |
| D | phy-qcom-usb-hsic.c | 11 #include <linux/phy/phy.h>
13 #include <linux/pinctrl/pinctrl-state.h>
22 struct phy *phy; member
29 static int qcom_usb_hsic_phy_power_on(struct phy *phy) in qcom_usb_hsic_phy_power_on() argument
31 struct qcom_usb_hsic_phy *uphy = phy_get_drvdata(phy); in qcom_usb_hsic_phy_power_on()
32 struct ulpi *ulpi = uphy->ulpi; in qcom_usb_hsic_phy_power_on()
36 ret = clk_prepare_enable(uphy->phy_clk); in qcom_usb_hsic_phy_power_on()
40 ret = clk_prepare_enable(uphy->cal_clk); in qcom_usb_hsic_phy_power_on()
44 ret = clk_prepare_enable(uphy->cal_sleep_clk); in qcom_usb_hsic_phy_power_on()
58 /* Configure pins for HSIC functionality */ in qcom_usb_hsic_phy_power_on()
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/usb/ |
| D | exynos-usb.txt | 8 - compatible: should be "samsung,exynos4210-ehci" for USB 2.0
10 - reg: physical base address of the controller and length of memory mapped
12 - interrupts: interrupt number to the cpu.
13 - clocks: from common clock binding: handle to usb clock.
14 - clock-names: from common clock binding: Shall be "usbhost".
15 - port: if in the SoC there are EHCI phys, they should be listed here.
16 One phy per port. Each port should have following entries:
17 - reg: port number on EHCI controller, e.g
18 On Exynos5250, port 0 is USB2.0 otg phy
19 port 1 is HSIC phy0
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/ |
| D | nvidia,tegra124-xusb.txt | 8 --------------------
9 - compatible: Must be:
10 - Tegra124: "nvidia,tegra124-xusb"
11 - Tegra132: "nvidia,tegra132-xusb", "nvidia,tegra124-xusb"
12 - Tegra210: "nvidia,tegra210-xusb"
13 - Tegra186: "nvidia,tegra186-xusb"
14 - reg: Must contain the base and length of the xHCI host registers, XUSB FPCI
16 - reg-names: Must contain the following entries:
17 - "hcd"
18 - "fpci"
[all …]
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