| /kernel/linux/linux-5.10/arch/riscv/boot/dts/sifive/ |
| D | fu540-c000.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V bindings for 'cpus' DT nodes
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 This document uses some terminology common to the RISC-V community
18 mandated by the RISC-V ISA: a PC and some registers. This
28 - items:
29 - enum:
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/riscv/ |
| D | cpus.txt | 2 RISC-V CPU Bindings
13 with updates for 32-bit and 64-bit RISC-V systems provided in this document.
19 This document uses some terminology common to the RISC-V community that is not
23 the RISC-V ISA: a PC and some registers. This terminology is designed to
33 The RISC-V architecture, in accordance with the Devicetree Specification,
37 - cpus node
45 - #address-cells
49 - #size-cells
54 - cpu node
60 - device_type
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| /kernel/linux/linux-5.10/arch/arc/mm/ |
| D | tlb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * TLB Management (flush/create/diagnostics) for ARC700
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
8 * -Reintroduce duplicate PD fixup - some customer chips still have the issue
11 * -No need to flush_cache_page( ) for each call to update_mmu_cache()
13 * = page-fault thrice as fast (75 usec to 28 usec)
18 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
22 * -MMU v2/v3 BCRs decoded differently
23 * -Remove TLB_SIZE hardcoding as it's variable now: 256 or 512
24 * -tlb_entry_erase( ) can be void
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| /kernel/linux/linux-4.19/arch/arc/mm/ |
| D | tlb.c | 2 * TLB Management (flush/create/diagnostics) for ARC700
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
11 * -Reintroduce duplicate PD fixup - some customer chips still have the issue
14 * -No need to flush_cache_page( ) for each call to update_mmu_cache()
16 * = page-fault thrice as fast (75 usec to 28 usec)
21 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
25 * -MMU v2/v3 BCRs decoded differently
26 * -Remove TLB_SIZE hardcoding as it's variable now: 256 or 512
27 * -tlb_entry_erase( ) can be void
28 * -local_flush_tlb_range( ):
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| /kernel/linux/linux-4.19/arch/sh/kernel/cpu/sh5/ |
| D | probe.c | 4 * CPU Subtype Probing for SH-5.
7 * Copyright (C) 2003 - 2007 Paul Mundt
18 #include <asm/tlb.h>
26 * the WPC registers. On SH5-101 cut2, such a mapping would be in cpu_probe()
34 /* CPU.VCR aliased at CIR address on SH5-101 */ in cpu_probe()
40 * First, setup some sane values for the I-cache. in cpu_probe()
43 boot_cpu_data.icache.sets = 256; in cpu_probe()
47 boot_cpu_data.icache.way_size = boot_cpu_data.icache.sets * in cpu_probe()
53 * Next, setup some sane values for the D-cache. in cpu_probe()
55 * On the SH5, these are pretty consistent with the I-cache settings, in cpu_probe()
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| /kernel/linux/linux-4.19/arch/powerpc/mm/ |
| D | tlb-radix.c | 2 * TLB flush routines for radix kernels.
4 * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
18 #include <asm/ppc-opcode.h>
19 #include <asm/tlb.h>
30 * i.e., r=1 and is=01 or is=10 or is=11
43 : : "r"(rb), "r"(rs), "i"(ric), "i"(prs) in tlbiel_radix_set_isa300()
54 * Flush the first set of the TLB, and the entire Page Walk Cache in tlbiel_all_isa300()
55 * and partition table entries. Then flush the remaining sets of the in tlbiel_all_isa300()
56 * TLB. in tlbiel_all_isa300()
88 WARN(1, "%s called on pre-POWER9 CPU\n", __func__); in radix__tlbiel_all()
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| D | init_32.c | 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8 * PPC44x/36-bit changes by Matt Porter (mporter@mvista.com)
45 #include <asm/tlb.h>
52 /* The amount of lowmem must be within 0xF0000000 - KERNELBASE. */
53 #if (CONFIG_LOWMEM_SIZE > (0xF0000000 - PAGE_OFFSET))
85 * (i.e. page tables) instead of the bats.
86 * -- Cort
95 * Check for command-line options that affect what MMU_init will do.
120 * MMU_init sets up the basic memory mappings for the kernel,
121 * including both RAM and possibly some I/O regions,
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| /kernel/linux/linux-4.19/arch/sh/mm/ |
| D | cache-sh5.c | 2 * arch/sh/mm/cache-sh5.c
7 * Copyright (C) 2003 - 2008 Paul Mundt
16 #include <asm/tlb.h>
25 /* Wired TLB entry for the D-cache */
73 /* Invalidate range of addresses [start,end] from the I-cache, where in sh64_icache_inv_kernel_range()
89 /* If we get called, we know that vma->vm_flags contains VM_EXEC. in sh64_icache_inv_user_page()
90 Also, eaddr is page-aligned. */ in sh64_icache_inv_user_page()
98 /* Check whether we can use the current ASID for the I-cache in sh64_icache_inv_user_page()
100 access_process_vm->flush_cache_page->here, (e.g. when reading from in sh64_icache_inv_user_page()
104 Also, note the risk that we might get pre-empted between the ASID in sh64_icache_inv_user_page()
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| /kernel/linux/linux-4.19/arch/powerpc/kernel/ |
| D | setup_64.c | 66 #include <asm/code-patching.h>
71 #include <asm/feature-fixups.h>
107 * If we boot via kdump on a non-primary thread, in setup_tlb_core_data()
109 * set up this TLB. in setup_tlb_core_data()
114 paca_ptrs[cpu]->tcd_ptr = &paca_ptrs[first]->tcd; in setup_tlb_core_data()
118 * or e6500 tablewalk mode, or else TLB handlers in setup_tlb_core_data()
134 /* Look for ibm,smt-enabled OF option */
161 smt_option = of_get_property(dn, "ibm,smt-enabled", in check_smt_enabled()
176 /* Look for smt-enabled= cmdline option */
182 early_param("smt-enabled", early_smt_enabled);
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| /kernel/linux/linux-5.10/arch/powerpc/include/asm/nohash/32/ |
| D | pte-44x.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
9 * Because of the 3 word TLB entries to support 36-bit addressing,
11 * are easily loaded during exception processing. I decided to
16 * ERPN fields in the TLB. -Matt
19 * easier to move into the TLB from the PTE. -BenH.
25 * PPC 440 core has following TLB attribute fields;
29 * RPN................................. - - - - - - ERPN.......
33 * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR
43 * into TLB entry.
45 * - PRESENT *must* be in the bottom three bits because swap cache
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| /kernel/linux/linux-5.10/arch/openrisc/mm/ |
| D | tlb.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * OpenRISC tlb.c
11 * Copyright (C) 2010-2011 Julius Baxter <julius.baxter@orsoc.se>
12 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
29 #define NO_CONTEXT -1
35 #define DTLB_OFFSET(addr) (((addr) >> PAGE_SHIFT) & (NUM_DTLB_SETS-1))
36 #define ITLB_OFFSET(addr) (((addr) >> PAGE_SHIFT) & (NUM_ITLB_SETS-1))
38 * Invalidate all TLB entries.
48 int i; in local_flush_tlb_all() local
51 /* Determine number of sets for IMMU. */ in local_flush_tlb_all()
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| /kernel/linux/linux-4.19/arch/openrisc/mm/ |
| D | tlb.c | 2 * OpenRISC tlb.c
10 * Copyright (C) 2010-2011 Julius Baxter <julius.baxter@orsoc.se>
11 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
35 #define NO_CONTEXT -1
41 #define DTLB_OFFSET(addr) (((addr) >> PAGE_SHIFT) & (NUM_DTLB_SETS-1))
42 #define ITLB_OFFSET(addr) (((addr) >> PAGE_SHIFT) & (NUM_ITLB_SETS-1))
44 * Invalidate all TLB entries.
54 int i; in local_flush_tlb_all() local
57 /* Determine number of sets for IMMU. */ in local_flush_tlb_all()
58 /* FIXME: Assumption is I & D nsets equal. */ in local_flush_tlb_all()
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| /kernel/linux/linux-5.10/arch/powerpc/kernel/ |
| D | setup_64.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
61 #include <asm/code-patching.h>
66 #include <asm/feature-fixups.h>
99 * If we boot via kdump on a non-primary thread, in setup_tlb_core_data()
101 * set up this TLB. in setup_tlb_core_data()
106 paca_ptrs[cpu]->tcd_ptr = &paca_ptrs[first]->tcd; in setup_tlb_core_data()
110 * or e6500 tablewalk mode, or else TLB handlers in setup_tlb_core_data()
126 /* Look for ibm,smt-enabled OF option */
153 smt_option = of_get_property(dn, "ibm,smt-enabled", in check_smt_enabled()
168 /* Look for smt-enabled= cmdline option */
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| /kernel/linux/linux-4.19/arch/parisc/include/asm/ |
| D | ropes.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <asm/parisc-device.h>
8 /* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */
30 void __iomem *ioc_hpa; /* I/O MMU base address */
33 unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */
34 unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */
38 unsigned long *res_hint; /* next avail IOVP - circular search */
85 unsigned int num_ioc; /* number of on-board IOC's */
96 return d->id.hversion == ASTRO_RUNWAY_PORT; in IS_ASTRO()
100 return d->id.hversion == IKE_MERCED_PORT; in IS_IKE()
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| /kernel/linux/linux-5.10/arch/parisc/include/asm/ |
| D | ropes.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <asm/parisc-device.h>
8 /* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */
30 void __iomem *ioc_hpa; /* I/O MMU base address */
33 unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */
34 unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */
38 unsigned long *res_hint; /* next avail IOVP - circular search */
85 unsigned int num_ioc; /* number of on-board IOC's */
96 return d->id.hversion == ASTRO_RUNWAY_PORT; in IS_ASTRO()
100 return d->id.hversion == IKE_MERCED_PORT; in IS_IKE()
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| /kernel/linux/linux-5.10/arch/mips/kvm/ |
| D | tlb.c | 6 * KVM/MIPS TLB handling, this file is part of the Linux host kernel so that
7 * TLB handlers run from KSEG0
26 #include <asm/tlb.h>
46 struct mm_struct *gpa_mm = &vcpu->kvm->arch.gpa_mm; in kvm_mips_get_root_asid()
57 struct mm_struct *kern_mm = &vcpu->arch.guest_kernel_mm; in kvm_mips_get_kernel_asid()
65 struct mm_struct *user_mm = &vcpu->arch.guest_user_mm; in kvm_mips_get_user_asid()
71 /* Structure defining an tlb entry data set. */
90 struct mips_coproc *cop0 = vcpu->arch.cop0; in kvm_mips_dump_guest_tlbs()
91 struct kvm_mips_tlb tlb; in kvm_mips_dump_guest_tlbs() local
92 int i; in kvm_mips_dump_guest_tlbs() local
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| /kernel/linux/linux-4.19/arch/mips/kvm/ |
| D | tlb.c | 6 * KVM/MIPS TLB handling, this file is part of the Linux host kernel so that
7 * TLB handlers run from KSEG0
26 #include <asm/tlb.h>
46 struct mm_struct *gpa_mm = &vcpu->kvm->arch.gpa_mm; in kvm_mips_get_root_asid()
57 struct mm_struct *kern_mm = &vcpu->arch.guest_kernel_mm; in kvm_mips_get_kernel_asid()
65 struct mm_struct *user_mm = &vcpu->arch.guest_user_mm; in kvm_mips_get_user_asid()
71 /* Structure defining an tlb entry data set. */
90 struct mips_coproc *cop0 = vcpu->arch.cop0; in kvm_mips_dump_guest_tlbs()
91 struct kvm_mips_tlb tlb; in kvm_mips_dump_guest_tlbs() local
92 int i; in kvm_mips_dump_guest_tlbs() local
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| /kernel/linux/linux-5.10/arch/powerpc/mm/ |
| D | init_32.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
9 * PPC44x/36-bit changes by Matt Porter (mporter@mvista.com)
38 #include <asm/tlb.h>
47 /* The amount of lowmem must be within 0xF0000000 - KERNELBASE. */
48 #if (CONFIG_LOWMEM_SIZE > (0xF0000000 - PAGE_OFFSET))
75 * (i.e. page tables) instead of the bats.
76 * -- Cort
85 * Check for command-line options that affect what MMU_init will do.
108 * MMU_init sets up the basic memory mappings for the kernel,
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| /kernel/linux/linux-4.19/arch/powerpc/include/asm/ |
| D | mmu.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
8 #include <asm/asm-const.h>
50 /* Enable >32-bit physical addresses on 32-bit processor, only used
55 /* Enable use of broadcast TLB invalidations. We don't always set it
77 /* Enable use of TLB reservation. Processor should support tlbsrx.
110 /* MMU feature bit sets for various CPUs */
152 return !!(MMU_FTRS_POSSIBLE & cur_cpu_spec->mmu_features & feature); in early_mmu_has_feature()
166 int i; in mmu_has_feature() local
183 i = __builtin_ctzl(feature); in mmu_has_feature()
184 return static_branch_likely(&mmu_feature_keys[i]); in mmu_has_feature()
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| /kernel/linux/linux-5.10/arch/powerpc/mm/book3s64/ |
| D | radix_tlb.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * TLB flush routines for radix kernels.
5 * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
14 #include <asm/ppc-opcode.h>
15 #include <asm/tlb.h>
27 * i.e., r=1 and is=01 or is=10 or is=11
40 : : "r"(rb), "r"(rs), "i"(ric), "i"(prs) in tlbiel_radix_set_isa300()
51 * Flush the first set of the TLB, and the entire Page Walk Cache in tlbiel_all_isa300()
52 * and partition table entries. Then flush the remaining sets of the in tlbiel_all_isa300()
53 * TLB. in tlbiel_all_isa300()
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| /kernel/linux/linux-5.10/arch/arm/mm/ |
| D | proc-arm720.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mm/proc-arm720.S: MMU functions for ARM720
8 * hacked for non-paged-MM by Hyok S. Choi, 2004.
10 * These are the low level assembler for performing cache and TLB
15 * 05-09-2000 SJH Created by moving 720 specific functions
16 * out of 'proc-arm6,7.S' per RMK discussion
17 * 07-25-2000 SJH Added idle function.
18 * 08-25-2000 DBS Updated for integration of ARM Ltd version.
19 * 04-20-2004 HSC modified for non-paged memory management mode.
25 #include <asm/asm-offsets.h>
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| /kernel/linux/linux-5.10/include/asm-generic/ |
| D | tlb.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* include/asm-generic/tlb.h
4 * Generic TLB shootdown code
32 * Generic MMU-gather implementation.
35 * correct and efficient ordering of freeing pages and TLB invalidations.
40 * 2) TLB invalidate page
49 * - tlb_gather_mmu() / tlb_finish_mmu(); start and finish a mmu_gather
51 * Finish in particular will issue a (final) TLB invalidate and free
54 * - tlb_start_vma() / tlb_end_vma(); marks the start / end of a VMA
59 * - tlb_remove_table()
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| /kernel/linux/linux-5.10/arch/powerpc/kvm/ |
| D | e500_mmu_host.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2008-2013 Freescale Semiconductor, Inc. All rights reserved.
30 #include <asm/pte-walk.h>
38 #define to_htlb1_esel(esel) (host_tlb_params[1].entries - (esel) - 1)
45 return host_tlb_params[1].entries - tlbcam_index - 1; in tlb1_max_shadow_size()
67 * writing shadow tlb entry to host TLB
77 mtspr(SPRN_MAS1, stlbe->mas1); in __write_host_tlbe()
78 mtspr(SPRN_MAS2, (unsigned long)stlbe->mas2); in __write_host_tlbe()
79 mtspr(SPRN_MAS3, (u32)stlbe->mas7_3); in __write_host_tlbe()
80 mtspr(SPRN_MAS7, (u32)(stlbe->mas7_3 >> 32)); in __write_host_tlbe()
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| /kernel/linux/linux-4.19/arch/powerpc/kvm/ |
| D | e500_mmu_host.c | 2 * Copyright (C) 2008-2013 Freescale Semiconductor, Inc. All rights reserved.
33 #include <asm/pte-walk.h>
41 #define to_htlb1_esel(esel) (host_tlb_params[1].entries - (esel) - 1)
48 return host_tlb_params[1].entries - tlbcam_index - 1; in tlb1_max_shadow_size()
70 * writing shadow tlb entry to host TLB
80 mtspr(SPRN_MAS1, stlbe->mas1); in __write_host_tlbe()
81 mtspr(SPRN_MAS2, (unsigned long)stlbe->mas2); in __write_host_tlbe()
82 mtspr(SPRN_MAS3, (u32)stlbe->mas7_3); in __write_host_tlbe()
83 mtspr(SPRN_MAS7, (u32)(stlbe->mas7_3 >> 32)); in __write_host_tlbe()
96 trace_kvm_booke206_stlb_write(mas0, stlbe->mas8, stlbe->mas1, in __write_host_tlbe()
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