| /kernel/linux/linux-5.10/arch/riscv/boot/dts/sifive/ |
| D | fu540-c000.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
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| /kernel/linux/linux-5.10/sound/pci/trident/ |
| D | trident_memory.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Trident 4DWave-NX memory page allocation (TLB area)
23 do { (trident)->tlb.entries[page] = cpu_to_le32((addr) & ~(SNDRV_TRIDENT_PAGE_SIZE-1)); \
24 (trident)->tlb.shadow_entries[page] = (ptr); } while (0)
26 (void*)((trident)->tlb.shadow_entries[page])
28 (dma_addr_t)le32_to_cpu((trident->tlb.entries[page]) & ~(SNDRV_TRIDENT_PAGE_SIZE - 1))
31 /* page size == SNDRV_TRIDENT_PAGE_SIZE */
32 #define ALIGN_PAGE_SIZE PAGE_SIZE /* minimum page size for allocation */
34 /* fill TLB entrie(s) corresponding to page with ptr */
36 /* fill TLB entrie(s) corresponding to page with silence pointer */
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| /kernel/linux/linux-4.19/sound/pci/trident/ |
| D | trident_memory.c | 6 * Trident 4DWave-NX memory page allocation (TLB area)
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
38 do { (trident)->tlb.entries[page] = cpu_to_le32((addr) & ~(SNDRV_TRIDENT_PAGE_SIZE-1)); \
39 (trident)->tlb.shadow_entries[page] = (ptr); } while (0)
41 (void*)((trident)->tlb.shadow_entries[page])
43 (dma_addr_t)le32_to_cpu((trident->tlb.entries[page]) & ~(SNDRV_TRIDENT_PAGE_SIZE - 1))
46 /* page size == SNDRV_TRIDENT_PAGE_SIZE */
47 #define ALIGN_PAGE_SIZE PAGE_SIZE /* minimum page size for allocation */
49 /* fill TLB entrie(s) corresponding to page with ptr */
51 /* fill TLB entrie(s) corresponding to page with silence pointer */
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| /kernel/linux/linux-4.19/arch/sparc/mm/ |
| D | hugetlbpage.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * SPARC64 Huge TLB page support.
18 #include <asm/tlb.h>
23 /* Slightly simplified from the non-hugepage variant because by
49 VM_BUG_ON(addr != -ENOMEM); in hugetlb_get_unmapped_area_bottomup()
65 struct mm_struct *mm = current->mm; in hugetlb_get_unmapped_area_topdown()
69 /* This should only ever run for 32-bit processes. */ in hugetlb_get_unmapped_area_topdown()
75 info.high_limit = mm->mmap_base; in hugetlb_get_unmapped_area_topdown()
82 * so fall back to the bottom-up function here. This scenario in hugetlb_get_unmapped_area_topdown()
87 VM_BUG_ON(addr != -ENOMEM); in hugetlb_get_unmapped_area_topdown()
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| /kernel/linux/linux-5.10/arch/sparc/mm/ |
| D | hugetlbpage.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * SPARC64 Huge TLB page support.
17 #include <asm/tlb.h>
22 /* Slightly simplified from the non-hugepage variant because by
48 VM_BUG_ON(addr != -ENOMEM); in hugetlb_get_unmapped_area_bottomup()
64 struct mm_struct *mm = current->mm; in hugetlb_get_unmapped_area_topdown()
68 /* This should only ever run for 32-bit processes. */ in hugetlb_get_unmapped_area_topdown()
74 info.high_limit = mm->mmap_base; in hugetlb_get_unmapped_area_topdown()
81 * so fall back to the bottom-up function here. This scenario in hugetlb_get_unmapped_area_topdown()
86 VM_BUG_ON(addr != -ENOMEM); in hugetlb_get_unmapped_area_topdown()
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| /kernel/linux/linux-5.10/arch/powerpc/mm/ |
| D | hugetlbpage.c | 2 * PPC Huge TLB Page Support for Kernel.
7 * Based on the IA-32 version:
23 #include <asm/tlb.h>
26 #include <asm/pte-walk.h>
32 #define PTE_T_ORDER (__builtin_ffs(sizeof(pte_basic_t)) - \
41 return __find_linux_pte(mm->pgd, addr, NULL, NULL); in huge_pte_offset()
50 int i; in __hugepte_alloc() local
55 num_hugepd = 1 << (pshift - pdshift); in __hugepte_alloc()
57 cachep = PGT_CACHE(pdshift - pshift); in __hugepte_alloc()
63 return -ENOMEM; in __hugepte_alloc()
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| /kernel/linux/linux-5.10/kernel/dma/ |
| D | swiotlb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * I/O TLBs (aka DMA address translation hardware).
9 * Copyright (C) 2000, 2003 Hewlett-Packard Co
10 * David Mosberger-Tang <davidm@hpl.hp.com>
12 * 03/05/07 davidm Switch from PCI-DMA to generic device DMA API.
14 * unnecessary i-cache flushing.
21 #define pr_fmt(fmt) "software IO TLB: " fmt
24 #include <linux/dma-direct.h>
25 #include <linux/dma-map-ops.h>
48 #include <linux/iommu-helper.h>
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| /kernel/linux/linux-4.19/arch/powerpc/mm/ |
| D | hugetlbpage.c | 2 * PPC Huge TLB Page Support for Kernel.
7 * Based on the IA-32 version:
25 #include <asm/tlb.h>
28 #include <asm/pte-walk.h>
52 return __find_linux_pte(mm->pgd, addr, NULL, NULL); in huge_pte_offset()
61 int i; in __hugepte_alloc() local
66 num_hugepd = 1 << (pshift - pdshift); in __hugepte_alloc()
68 cachep = PGT_CACHE(pdshift - pshift); in __hugepte_alloc()
78 return -ENOMEM; in __hugepte_alloc()
89 * We have multiple higher-level entries that point to the same in __hugepte_alloc()
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| D | tlb_hash64.c | 3 * TLB and MMU hash table.
6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
30 #include <asm/tlb.h>
32 #include <asm/pte-walk.h>
54 int i, offset; in hpte_need_flush() local
56 i = batch->index; in hpte_need_flush()
58 /* Get page size (maybe move back to caller). in hpte_need_flush()
61 * for SPEs, we obtain the page size from the slice, which thus in hpte_need_flush()
68 /* Mask the address for the correct page size */ in hpte_need_flush()
69 addr &= ~((1UL << mmu_psize_defs[psize].shift) - 1); in hpte_need_flush()
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| D | 44x_mmu.c | 7 * -- paulus
10 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
35 /* Used by the 44x TLB replacement exception handler.
39 unsigned int tlb_44x_hwater = PPC44x_TLB_SIZE - 1 - PPC44x_EARLY_TLBS;
49 /* The TLB miss handlers hard codes the watermark in a cmpli in ppc44x_update_tlb_hwater()
52 * in the 2 TLB miss handlers when updating the value in ppc44x_update_tlb_hwater()
65 * "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 44x type MMU
69 unsigned int entry = tlb_44x_hwater--; in ppc44x_pin_tlb()
84 "i" (PPC44x_TLB_PAGEID), in ppc44x_pin_tlb()
85 "i" (PPC44x_TLB_XLAT), in ppc44x_pin_tlb()
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| D | tlb_nohash.c | 2 * This file contains the routines for TLB flushing.
5 * this does -not- include 603 however which shares the implementation with
8 * -- BenH
14 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
43 #include <asm/tlb.h>
44 #include <asm/code-patching.h>
52 * This struct lists the sw-supported page sizes. The hardawre MMU may support
155 /* The variables below are currently only used on 64-bit Book3E
161 int mmu_linear_psize; /* Page size used for the linear mapping */
162 int mmu_pte_psize; /* Page size used for PTE pages */
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| /kernel/linux/linux-5.10/include/asm-generic/ |
| D | tlb.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* include/asm-generic/tlb.h
4 * Generic TLB shootdown code
32 * Generic MMU-gather implementation.
35 * correct and efficient ordering of freeing pages and TLB invalidations.
40 * 2) TLB invalidate page
49 * - tlb_gather_mmu() / tlb_finish_mmu(); start and finish a mmu_gather
51 * Finish in particular will issue a (final) TLB invalidate and free
54 * - tlb_start_vma() / tlb_end_vma(); marks the start / end of a VMA
59 * - tlb_remove_table()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V bindings for 'cpus' DT nodes
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 This document uses some terminology common to the RISC-V community
18 mandated by the RISC-V ISA: a PC and some registers. This
28 - items:
29 - enum:
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| /kernel/linux/linux-4.19/kernel/dma/ |
| D | swiotlb.c | 5 * I/O TLBs (aka DMA address translation hardware).
8 * Copyright (C) 2000, 2003 Hewlett-Packard Co
9 * David Mosberger-Tang <davidm@hpl.hp.com>
11 * 03/05/07 davidm Switch from PCI-DMA to generic device DMA API.
13 * unnecessary i-cache flushing.
20 #define pr_fmt(fmt) "software IO TLB: " fmt
23 #include <linux/dma-direct.h>
43 #include <linux/iommu-helper.h>
49 ( (val) & ( (align) - 1)))
51 #define SLABS_PER_PAGE (1 << (PAGE_SHIFT - IO_TLB_SHIFT))
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/riscv/ |
| D | cpus.txt | 2 RISC-V CPU Bindings
13 with updates for 32-bit and 64-bit RISC-V systems provided in this document.
19 This document uses some terminology common to the RISC-V community that is not
23 the RISC-V ISA: a PC and some registers. This terminology is designed to
33 The RISC-V architecture, in accordance with the Devicetree Specification,
37 - cpus node
45 - #address-cells
49 - #size-cells
54 - cpu node
60 - device_type
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| /kernel/linux/linux-5.10/arch/powerpc/mm/book3s64/ |
| D | hash_tlb.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * TLB and MMU hash table.
7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
25 #include <asm/tlb.h>
27 #include <asm/pte-walk.h>
49 int i, offset; in hpte_need_flush() local
51 i = batch->index; in hpte_need_flush()
54 * Get page size (maybe move back to caller). in hpte_need_flush()
57 * for SPEs, we obtain the page size from the slice, which thus in hpte_need_flush()
64 /* Mask the address for the correct page size */ in hpte_need_flush()
[all …]
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| /kernel/linux/linux-4.19/Documentation/core-api/ |
| D | cachetlb.rst | 2 Cache and TLB Flushing Under Linux
7 This document describes the cache/tlb flushing interfaces called
17 thinking SMP cache/tlb flushing must be so inefficient, this is in
23 First, the TLB flushing interfaces, since they are the simplest. The
24 "TLB" is abstracted under Linux as something the cpu uses to cache
25 virtual-->physical address translations obtained from the software
27 possible for stale translations to exist in this "TLB" cache.
44 the TLB. After running, this interface must make sure that
47 there will be no entries in the TLB for 'mm'.
57 address translations from the TLB. After running, this
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| /kernel/linux/linux-5.10/arch/nios2/kernel/ |
| D | cpuinfo.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
41 if (!of_property_read_bool(cpu, "altr,has-initda")) in setup_cpuinfo()
43 "hardware system to have more than 4-byte line data " in setup_cpuinfo()
46 cpuinfo.cpu_clock_freq = fcpu(cpu, "clock-frequency"); in setup_cpuinfo()
54 cpuinfo.has_div = of_property_read_bool(cpu, "altr,has-div"); in setup_cpuinfo()
55 cpuinfo.has_mul = of_property_read_bool(cpu, "altr,has-mul"); in setup_cpuinfo()
56 cpuinfo.has_mulx = of_property_read_bool(cpu, "altr,has-mulx"); in setup_cpuinfo()
57 cpuinfo.has_bmx = of_property_read_bool(cpu, "altr,has-bmx"); in setup_cpuinfo()
58 cpuinfo.has_cdx = of_property_read_bool(cpu, "altr,has-cdx"); in setup_cpuinfo()
59 cpuinfo.mmu = of_property_read_bool(cpu, "altr,has-mmu"); in setup_cpuinfo()
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| /kernel/linux/linux-5.10/arch/powerpc/mm/nohash/ |
| D | 44x.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * -- paulus
11 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
27 #include <asm/code-patching.h>
31 /* Used by the 44x TLB replacement exception handler.
35 unsigned int tlb_44x_hwater = PPC44x_TLB_SIZE - 1 - PPC44x_EARLY_TLBS;
42 /* The TLB miss handlers hard codes the watermark in a cmpli in ppc44x_update_tlb_hwater()
45 * in the 2 TLB miss handlers when updating the value in ppc44x_update_tlb_hwater()
52 * "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 44x type MMU
56 unsigned int entry = tlb_44x_hwater--; in ppc44x_pin_tlb()
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| D | tlb.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * This file contains the routines for TLB flushing.
6 * this does -not- include 603 however which shares the implementation with
9 * -- BenH
15 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
39 #include <asm/tlb.h>
40 #include <asm/code-patching.h>
48 * This struct lists the sw-supported page sizes. The hardawre MMU may support
147 /* The variables below are currently only used on 64-bit Book3E
153 int mmu_linear_psize; /* Page size used for the linear mapping */
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| /kernel/linux/linux-5.10/Documentation/core-api/ |
| D | cachetlb.rst | 2 Cache and TLB Flushing Under Linux
7 This document describes the cache/tlb flushing interfaces called
17 thinking SMP cache/tlb flushing must be so inefficient, this is in
23 First, the TLB flushing interfaces, since they are the simplest. The
24 "TLB" is abstracted under Linux as something the cpu uses to cache
25 virtual-->physical address translations obtained from the software
27 possible for stale translations to exist in this "TLB" cache.
44 the TLB. After running, this interface must make sure that
47 there will be no entries in the TLB for 'mm'.
57 address translations from the TLB. After running, this
[all …]
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| /kernel/linux/linux-4.19/arch/nios2/kernel/ |
| D | cpuinfo.c | 54 if (!of_property_read_bool(cpu, "altr,has-initda")) in setup_cpuinfo()
56 "hardware system to have more than 4-byte line data " in setup_cpuinfo()
59 cpuinfo.cpu_clock_freq = fcpu(cpu, "clock-frequency"); in setup_cpuinfo()
67 cpuinfo.has_div = of_property_read_bool(cpu, "altr,has-div"); in setup_cpuinfo()
68 cpuinfo.has_mul = of_property_read_bool(cpu, "altr,has-mul"); in setup_cpuinfo()
69 cpuinfo.has_mulx = of_property_read_bool(cpu, "altr,has-mulx"); in setup_cpuinfo()
70 cpuinfo.has_bmx = of_property_read_bool(cpu, "altr,has-bmx"); in setup_cpuinfo()
71 cpuinfo.has_cdx = of_property_read_bool(cpu, "altr,has-cdx"); in setup_cpuinfo()
72 cpuinfo.mmu = of_property_read_bool(cpu, "altr,has-mmu"); in setup_cpuinfo()
89 cpuinfo.tlb_num_ways = fcpu(cpu, "altr,tlb-num-ways"); in setup_cpuinfo()
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| /kernel/linux/linux-5.10/arch/microblaze/include/asm/ |
| D | mmu.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2008-2009 PetaLogix
12 # include <asm-generic/mmu.h>
30 unsigned long w:1; /* Write-thru cache mode */
31 unsigned long i:1; /* Cache inhibited */ member
46 unsigned long t:1; /* Normal or I/O type */
49 unsigned long n:1; /* No-execute */
54 extern void _tlbie(unsigned long va); /* invalidate a TLB entry */
55 extern void _tlbia(void); /* invalidate all TLB entries */
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| /kernel/linux/linux-5.10/drivers/parisc/ |
| D | ccio-dma.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 ** ccio-dma.c:
4 ** DMA management routines for first generation cache-coherent machines.
5 ** Program U2/Uturn in "Virtual Mode" and use the I/O MMU.
9 ** (c) Copyright 2000 Hewlett-Packard Company
15 ** the I/O MMU - basically what x86 does.
17 ** Philipp Rumpf has a "Real Mode" driver for PCX-W machines at:
18 ** CVSROOT=:pserver:anonymous@198.186.203.37:/cvsroot/linux-parisc
19 ** cvs -z3 co linux/arch/parisc/kernel/dma-rm.c
21 ** I've rewritten his code to work under TPG's tree. See ccio-rm-dma.c.
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| /kernel/linux/linux-4.19/drivers/parisc/ |
| D | ccio-dma.c | 2 ** ccio-dma.c:
3 ** DMA management routines for first generation cache-coherent machines.
4 ** Program U2/Uturn in "Virtual Mode" and use the I/O MMU.
8 ** (c) Copyright 2000 Hewlett-Packard Company
18 ** the I/O MMU - basically what x86 does.
20 ** Philipp Rumpf has a "Real Mode" driver for PCX-W machines at:
21 ** CVSROOT=:pserver:anonymous@198.186.203.37:/cvsroot/linux-parisc
22 ** cvs -z3 co linux/arch/parisc/kernel/dma-rm.c
24 ** I've rewritten his code to work under TPG's tree. See ccio-rm-dma.c.
27 ** o outbound DMA is slower - U2 won't prefetch data (GSC+ XQL signal).
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|