Searched +full:i2c +full:- +full:controller +full:- +full:id (Results 1 – 25 of 1079) sorted by relevance
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/mediatek/ |
| D | mt6797.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/clock/mt6797-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/mt6797-pinfunc.h>
14 interrupt-parent = <&sysirq>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <1>;
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| /kernel/linux/linux-5.10/drivers/i2c/busses/ |
| D | i2c-cadence.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * I2C bus driver for the Cadence I2C controller.
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
10 #include <linux/i2c.h>
18 /* Register offsets for the I2C device. */
21 #define CDNS_I2C_ADDR_OFFSET 0x08 /* I2C Address Register, RW */
22 #define CDNS_I2C_DATA_OFFSET 0x0C /* I2C Data Register, RW */
57 * I2C Address Register Bit mask definitions
59 * bits. A write access to this register always initiates a transfer if the I2C
62 #define CDNS_I2C_ADDR_MASK 0x000003FF /* I2C Address Mask */
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| D | i2c-designware-pcidrv.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Synopsys DesignWare I2C adapter driver (master only).
5 * Based on the TI DAVINCI I2C adapter driver.
16 #include <linux/i2c.h>
26 #include "i2c-designware-core.h"
28 #define DRIVER_NAME "i2c-designware-pci"
88 struct dw_i2c_dev *dev = dev_get_drvdata(&pdev->dev); in mfld_setup()
90 switch (pdev->device) { in mfld_setup()
92 dev->timings.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ; in mfld_setup()
96 c->bus_num = pdev->device - 0x817 + 3; in mfld_setup()
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/i2c/ |
| D | nvidia,tegra186-bpmp-i2c.txt | 1 NVIDIA Tegra186 BPMP I2C controller
4 devices, such as the I2C controller for the power management I2C bus. Software
6 transactions on that I2C bus. This binding describes an I2C bus that is
9 The BPMP I2C node must be located directly inside the main BPMP node. See
10 ../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding.
12 This node represents an I2C controller. See ../i2c/i2c.txt for details of the
13 core I2C binding.
16 - compatible:
19 - "nvidia,tegra186-bpmp-i2c".
20 - #address-cells: Address cells for I2C device address.
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| D | i2c-pxa-pci-ce4100.txt | 1 CE4100 I2C
2 ----------
4 CE4100 has one PCI device which is described as the I2C-Controller. This
5 PCI device has three PCI-bars, each bar contains a complete I2C
6 controller. So we have a total of three independent I2C-Controllers
8 The driver is probed via the PCI-ID and is gathering the information of
10 Grant Likely recommended to use the ranges property to map the PCI-Bar
12 of the specific I2C controller. This were his exact words:
22 non-zero if you had 2 or more devices mapped off
30 ------------------------------------------------
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| D | i2c-stm32.txt | 1 * I2C controller embedded in STMicroelectronics STM32 I2C platform
4 - compatible : Must be one of the following
5 - "st,stm32f4-i2c"
6 - "st,stm32f7-i2c"
7 - reg : Offset and length of the register set for the device
8 - interrupts : Must contain the interrupt id for I2C event and then the
9 interrupt id for I2C error.
10 - resets: Must contain the phandle to the reset controller.
11 - clocks: Must contain the input clock of the I2C instance.
12 - A pinctrl state named "default" must be defined to set pins in mode of
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/i2c/ |
| D | nvidia,tegra186-bpmp-i2c.txt | 1 NVIDIA Tegra186 BPMP I2C controller
4 devices, such as the I2C controller for the power management I2C bus. Software
6 transactions on that I2C bus. This binding describes an I2C bus that is
9 The BPMP I2C node must be located directly inside the main BPMP node. See
10 ../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding.
12 This node represents an I2C controller. See ../i2c/i2c.txt for details of the
13 core I2C binding.
16 - compatible:
19 - "nvidia,tegra186-bpmp-i2c".
20 - #address-cells: Address cells for I2C device address.
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| D | i2c-rk3x.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-rk3x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip RK3xxx I2C controller
10 This driver interfaces with the native I2C controller present in Rockchip
14 - $ref: /schemas/i2c/i2c-controller.yaml#
17 - Heiko Stuebner <heiko@sntech.de>
23 - const: rockchip,rv1108-i2c
24 - const: rockchip,rk3066-i2c
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| D | st,stm32-i2c.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/st,stm32-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: I2C controller embedded in STMicroelectronics STM32 I2C platform
10 - Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
14 - if:
19 - st,stm32f7-i2c
20 - st,stm32mp15-i2c
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| D | i2c-pxa.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-pxa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell MMP I2C controller bindings
10 - Rob Herring <robh+dt@kernel.org>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
14 - if:
17 - mrvl,i2c-polling
20 - interrupts
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| D | cdns,i2c-r1p10.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/i2c/cdns,i2c-r1p10.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Cadence I2C controller Device Tree Bindings
10 - Michal Simek <michal.simek@xilinx.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - cdns,i2c-r1p10 # cadence i2c controller version 1.0
19 - cdns,i2c-r1p14 # cadence i2c controller version 1.4
30 clock-frequency:
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| D | nuvoton,npcm7xx-i2c.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/i2c/nuvoton,npcm7xx-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: nuvoton NPCM7XX I2C Controller Device Tree Bindings
10 The NPCM750x includes sixteen I2C bus controllers. All Controllers support
11 both master and slave mode. Each controller can switch between master and slave
12 at run time (i.e. IPMB mode). Each controller has two 16 byte HW FIFO for TX and
16 - Tali Perry <tali.perry1@gmail.com>
20 const: nuvoton,npcm7xx-i2c
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| D | i2c-pxa-pci-ce4100.txt | 1 CE4100 I2C
2 ----------
4 CE4100 has one PCI device which is described as the I2C-Controller. This
5 PCI device has three PCI-bars, each bar contains a complete I2C
6 controller. So we have a total of three independent I2C-Controllers
8 The driver is probed via the PCI-ID and is gathering the information of
10 Grant Likely recommended to use the ranges property to map the PCI-Bar
12 of the specific I2C controller. This were his exact words:
22 non-zero if you had 2 or more devices mapped off
30 ------------------------------------------------
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| D | ingenic,i2c.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/ingenic,i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs I2C controller devicetree bindings
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
17 pattern: "^i2c@[0-9a-f]+$"
21 - enum:
22 - ingenic,jz4770-i2c
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| D | snps,designware-i2c.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/i2c/snps,designware-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare APB I2C Controller
10 - Jarkko Nikula <jarkko.nikula@linux.intel.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
14 - if:
19 const: mscc,ocelot-i2c
28 - description: Generic Synopsys DesignWare I2C controller
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| D | i2c-imx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-imx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Inter IC (I2C) and High Speed Inter IC (HS-I2C) for i.MX
10 - Wolfram Sang <wolfram@the-dreams.de>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - const: fsl,imx1-i2c
19 - const: fsl,imx21-i2c
20 - const: fsl,vf610-i2c
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| /kernel/linux/linux-4.19/drivers/i2c/busses/ |
| D | i2c-cadence.c | 2 * I2C bus driver for the Cadence I2C controller.
4 * Copyright (C) 2009 - 2014 Xilinx, Inc.
15 #include <linux/i2c.h>
23 /* Register offsets for the I2C device. */
26 #define CDNS_I2C_ADDR_OFFSET 0x08 /* I2C Address Register, RW */
27 #define CDNS_I2C_DATA_OFFSET 0x0C /* I2C Data Register, RW */
53 * I2C Address Register Bit mask definitions
55 * bits. A write access to this register always initiates a transfer if the I2C
58 #define CDNS_I2C_ADDR_MASK 0x000003FF /* I2C Address Mask */
61 * I2C Interrupt Registers Bit mask definitions
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| D | i2c-designware-pcidrv.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Synopsys DesignWare I2C adapter driver (master only).
5 * Based on the TI DAVINCI I2C adapter driver.
16 #include <linux/i2c.h>
26 #include "i2c-designware-core.h"
28 #define DRIVER_NAME "i2c-designware-pci"
90 switch (pdev->device) { in mfld_setup()
92 c->bus_cfg &= ~DW_IC_CON_SPEED_MASK; in mfld_setup()
93 c->bus_cfg |= DW_IC_CON_SPEED_STD; in mfld_setup()
97 c->bus_num = pdev->device - 0x817 + 3; in mfld_setup()
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/fsi/ |
| D | fsi.txt | 4 The FSI bus is probe-able, so the OS is able to enumerate FSI slaves, and
6 nodes to probed engines. This allows for fsi engines to expose non-probeable
8 that is an I2C master - the I2C bus can be described by the device tree under
13 the fsi-master-* binding specifications.
18 fsi-master {
19 /* top-level of FSI bus topology, bound to an FSI master driver and
22 fsi-slave@<link,id> {
26 fsi-slave-engine@<addr> {
32 fsi-slave-engine@<addr> {
39 Note that since the bus is probe-able, some (or all) of the topology may
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/fsi/ |
| D | fsi.txt | 4 The FSI bus is probe-able, so the OS is able to enumerate FSI slaves, and
6 nodes to probed engines. This allows for fsi engines to expose non-probeable
8 that is an I2C master - the I2C bus can be described by the device tree under
13 the fsi-master-* binding specifications.
18 fsi-master {
19 /* top-level of FSI bus topology, bound to an FSI master driver and
22 fsi-slave@<link,id> {
26 fsi-slave-engine@<addr> {
32 fsi-slave-engine@<addr> {
39 Note that since the bus is probe-able, some (or all) of the topology may
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/ti/ |
| D | k3-j7200-main.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 atf-sram@0 {
21 scm_conf: scm-conf@100000 {
22 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
24 #address-cells = <1>;
25 #size-cells = <1>;
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| /kernel/linux/linux-5.10/include/linux/i3c/ |
| D | master.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
14 #include <linux/i2c.h>
31 * struct i3c_i2c_dev_desc - Common part of the I3C/I2C device descriptor
32 * @node: node element used to insert the slot into the I2C or I3C device
35 * I2C/I3C transfers
39 * This structure is describing common I3C/I2C dev information.
54 * struct i2c_dev_boardinfo - I2C device board information
55 * @node: used to insert the boardinfo object in the I2C boardinfo list
56 * @base: regular I2C board information
58 * the I2C device limitations
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| /kernel/linux/linux-5.10/Documentation/i2c/busses/ |
| D | i2c-i801.rst | 2 Kernel driver i2c-i801
7 * Intel 82801AA and 82801AB (ICH and ICH0 - part of the
9 * Intel 82801BA (ICH2 - part of the '815E' chipset)
51 On Intel Patsburg and later chipsets, both the normal host SMBus controller
55 - Mark Studebaker <mdsxyz123@yahoo.com>
56 - Jean Delvare <jdelvare@suse.de>
60 -----------------
71 0x08 disable the I2C block read functionality
78 -----------
82 Intel's '810' chipset for Celeron-based PCs, '810E' chipset for
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| /kernel/linux/linux-4.19/drivers/input/touchscreen/ |
| D | bu21013_ts.c | 2 * Copyright (C) ST-Ericsson SA 2010
3 * Author: Naveen Kumar G <naveen.gaddipati@stericsson.com> for ST-Ericsson
10 #include <linux/i2c.h>
140 * struct bu21013_ts_data - touch panel data structure
141 * @client: pointer to the i2c client
144 * @chip: pointer to the touch panel controller
163 * bu21013_read_block_data(): read the touch co-ordinates
167 * Read the touch co-ordinates using i2c read block into buffer
176 (data->client, BU21013_SENSORS_BTN_0_7_REG, in bu21013_read_block_data()
181 return -EINVAL; in bu21013_read_block_data()
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/tegra/ |
| D | nvidia,tegra20-pmc.txt | 1 NVIDIA Tegra Power Management Controller (PMC)
3 == Power Management Controller Node ==
7 modes. It provides power-gating controllers for SoC and CPU power-islands.
10 - name : Should be pmc
11 - compatible : Should contain one of the following:
12 For Tegra20 must contain "nvidia,tegra20-pmc".
13 For Tegra30 must contain "nvidia,tegra30-pmc".
14 For Tegra114 must contain "nvidia,tegra114-pmc"
15 For Tegra124 must contain "nvidia,tegra124-pmc"
16 For Tegra132 must contain "nvidia,tegra124-pmc"
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