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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/i2c/
Dcdns,i2c-r1p10.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/i2c/cdns,i2c-r1p10.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Cadence I2C controller Device Tree Bindings
10 - Michal Simek <michal.simek@xilinx.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - cdns,i2c-r1p10 # cadence i2c controller version 1.0
19 - cdns,i2c-r1p14 # cadence i2c controller version 1.4
30 clock-frequency:
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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/i2c/
Di2c-cadence.txt1 Binding for the Cadence I2C controller
4 - reg: Physical base address and size of the controller's register area.
5 - compatible: Should contain one of:
6 * "cdns,i2c-r1p10"
7 Note: Use this when cadence i2c controller version 1.0 is used.
8 * "cdns,i2c-r1p14"
9 Note: Use this when cadence i2c controller version 1.4 is used.
10 - clocks: Input clock specifier. Refer to common clock bindings.
11 - interrupts: Interrupt specifier. Refer to interrupt bindings.
12 - #address-cells: Should be 1.
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/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
20 clock-latency = <1000>;
21 cpu0-supply = <&regulator_vccpint>;
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
20 clock-latency = <1000>;
21 cpu0-supply = <&regulator_vccpint>;
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/kernel/linux/linux-4.19/drivers/i2c/busses/
Di2c-cadence.c2 * I2C bus driver for the Cadence I2C controller.
4 * Copyright (C) 2009 - 2014 Xilinx, Inc.
15 #include <linux/i2c.h>
23 /* Register offsets for the I2C device. */
26 #define CDNS_I2C_ADDR_OFFSET 0x08 /* I2C Address Register, RW */
27 #define CDNS_I2C_DATA_OFFSET 0x0C /* I2C Data Register, RW */
53 * I2C Address Register Bit mask definitions
55 * bits. A write access to this register always initiates a transfer if the I2C
58 #define CDNS_I2C_ADDR_MASK 0x000003FF /* I2C Address Mask */
61 * I2C Interrupt Registers Bit mask definitions
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/kernel/linux/linux-5.10/drivers/i2c/busses/
Di2c-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * I2C bus driver for the Cadence I2C controller.
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
10 #include <linux/i2c.h>
18 /* Register offsets for the I2C device. */
21 #define CDNS_I2C_ADDR_OFFSET 0x08 /* I2C Address Register, RW */
22 #define CDNS_I2C_DATA_OFFSET 0x0C /* I2C Data Register, RW */
57 * I2C Address Register Bit mask definitions
59 * bits. A write access to this register always initiates a transfer if the I2C
62 #define CDNS_I2C_ADDR_MASK 0x000003FF /* I2C Address Mask */
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/kernel/linux/linux-5.10/
DMAINTAINERS9 -------------------------
30 ``diff -u`` to make the patch easy to merge. Be prepared to get your
40 See Documentation/process/coding-style.rst for guidance here.
46 See Documentation/process/submitting-patches.rst for details.
57 include a Signed-off-by: line. The current version of this
59 Documentation/process/submitting-patches.rst.
70 that the bug would present a short-term risk to other users if it
76 Documentation/admin-guide/security-bugs.rst for details.
81 ---------------------------------------------------
97 W: *Web-page* with status/info
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