| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | imx7ulp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
8 #include <dt-bindings/clock/imx7ulp-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx7ulp-pinfunc.h"
15 interrupt-parent = <&intc>;
17 #address-cells = <1>;
18 #size-cells = <1>;
37 #address-cells = <1>;
[all …]
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| D | imx7ulp-com.dts | 1 // SPDX-License-Identifier: GPL-2.0
5 /dts-v1/;
7 #include "imx7ulp.dtsi"
8 #include <dt-bindings/input/input.h>
12 compatible = "ea,imx7ulp-com", "fsl,imx7ulp";
15 stdout-path = &lpuart4;
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_lpuart4>;
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_usbotg1_id>;
[all …]
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| D | imx7ulp-evk.dts | 1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
8 /dts-v1/;
10 #include "imx7ulp.dtsi"
14 compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp";
17 stdout-path = &lpuart4;
26 compatible = "pwm-backlight";
28 brightness-levels = <0 20 25 30 35 40 100>;
29 default-brightness-level = <6>;
33 reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | imx7ulp-pcc-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx7ulp-pcc-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Clock bindings for Freescale i.MX7ULP Peripheral Clock Control (PCC) modules
10 - A.s. Dong <aisheng.dong@nxp.com>
13 i.MX7ULP Clock functions are under joint control of the System
14 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
18 and A7 domain. Except for a few clock sources shared between two
19 domains, such as the System Oscillator clock, the Slow IRC (SIRC),
[all …]
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| D | imx7ulp-scg-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx7ulp-scg-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Clock bindings for Freescale i.MX7ULP System Clock Generation (SCG) modules
10 - A.s. Dong <aisheng.dong@nxp.com>
13 i.MX7ULP Clock functions are under joint control of the System
14 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
18 and A7 domain. Except for a few clock sources shared between two
19 domains, such as the System Oscillator clock, the Slow IRC (SIRC),
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/i2c/ |
| D | i2c-imx-lpi2c.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-imx-lpi2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anson Huang <Anson.Huang@nxp.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - enum:
19 - fsl,imx7ulp-lpi2c
20 - fsl,imx8qm-lpi2c
21 - items:
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/watchdog/ |
| D | fsl-imx7ulp-wdt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/fsl-imx7ulp-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anson Huang <Anson.Huang@nxp.com>
13 - $ref: "watchdog.yaml#"
18 - fsl,imx7ulp-wdt
29 assigned-clocks:
32 assigned-clocks-parents:
35 timeout-sec: true
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/ |
| D | nxp,tpm-timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nxp,tpm-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
16 are clocked by an asynchronous clock that can remain enabled in low
22 const: fsl,imx7ulp-tpm
32 - description: SoC TPM ipg clock
33 - description: SoC TPM per clock
35 clock-names:
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pwm/ |
| D | imx-tpm-pwm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/imx-tpm-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anson Huang <anson.huang@nxp.com>
17 "#pwm-cells":
22 - fsl,imx7ulp-pwm
27 assigned-clocks:
30 assigned-clock-parents:
37 - "#pwm-cells"
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/ |
| D | spi-fsl-lpspi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-fsl-lpspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anson Huang <Anson.Huang@nxp.com>
13 - $ref: "/schemas/spi/spi-controller.yaml#"
18 - fsl,imx7ulp-spi
19 - fsl,imx8qxp-spi
29 - description: SoC SPI per clock
30 - description: SoC SPI ipg clock
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/timer/ |
| D | nxp,tpm-timer.txt | 6 are clocked by an asynchronous clock that can remain enabled in low
12 - compatible : should be "fsl,imx7ulp-tpm"
13 - reg : Specifies base physical address and size of the register sets
14 for the clock event device and clock source device.
15 - interrupts : Should be the clock event device interrupt.
16 - clocks : The clocks provided by the SoC to drive the timer, must contain
17 an entry for each entry in clock-names.
18 - clock-names : Must include the following entries: "ipg" and "per".
22 compatible = "fsl,imx7ulp-tpm";
27 clock-names = "ipg", "per";
|
| /kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/ |
| D | imx8qxp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
8 #include <dt-bindings/clock/imx8-clock.h>
9 #include <dt-bindings/firmware/imx/rsrc.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
14 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/serial/ |
| D | fsl-lpuart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/fsl-lpuart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fugang Duan <fugang.duan@nxp.com>
13 - $ref: "rs485.yaml"
18 - enum:
19 - fsl,vf610-lpuart
20 - fsl,ls1021a-lpuart
21 - fsl,ls1028a-lpuart
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/spi/ |
| D | spi-fsl-lpspi.txt | 4 - compatible :
5 - "fsl,imx7ulp-spi" for LPSPI compatible with the one integrated on i.MX7ULP soc
6 - reg : address and length of the lpspi master registers
7 - interrupts : lpspi interrupt
8 - clocks : lpspi clock specifier
13 compatible = "fsl,imx7ulp-spi";
15 interrupt-parent = <&intc>;
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/i2c/ |
| D | i2c-imx-lpi2c.txt | 4 - compatible :
5 - "fsl,imx7ulp-lpi2c" for LPI2C compatible with the one integrated on i.MX7ULP soc
6 - reg : address and length of the lpi2c master registers
7 - interrupts : lpi2c interrupt
8 - clocks : lpi2c clock specifier
13 compatible = "fsl,imx7ulp-lpi2c";
15 interrupt-parent = <&intc>;
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/ |
| D | fsl-edma.txt | 3 The eDMA channels have multiplex capability by programmble memory-mapped
10 - compatible :
11 - "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC
12 - "fsl,imx7ulp-edma" for eDMA2 used similar to that on i.mx7ulp
13 - "fsl,ls1028a-edma" followed by "fsl,vf610-edma" for eDMA used on the
15 - reg : Specifies base physical address(s) and size of the eDMA registers.
19 - interrupts : A list of interrupt-specifiers, one for each entry in
20 interrupt-names on vf610 similar SoC. But for i.mx7ulp per channel
22 error interrupt(located in the last), no interrupt-names list on
24 - #dma-cells : Must be <2>.
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/imx/ |
| D | clk-imx7ulp.c | 1 // SPDX-License-Identifier: GPL-2.0+
10 #include <dt-bindings/clock/imx7ulp-clock.h>
11 #include <linux/clk-provider.h>
57 clk_data->num = IMX7ULP_CLK_SCG1_END; in imx7ulp_clk_scg1_init()
58 hws = clk_data->hws; in imx7ulp_clk_scg1_init()
104 /* scs/ddr/nic select different clock source requires that clock to be enabled first */ in imx7ulp_clk_scg1_init()
111 …re", hws[IMX7ULP_CLK_CORE_DIV]->clk, hws[IMX7ULP_CLK_SYS_SEL]->clk, hws[IMX7ULP_CLK_SPLL_SEL]->clk… in imx7ulp_clk_scg1_init()
113 …IMX7ULP_CLK_HSRUN_CORE_DIV]->clk, hws[IMX7ULP_CLK_HSRUN_SYS_SEL]->clk, hws[IMX7ULP_CLK_SPLL_SEL]->… in imx7ulp_clk_scg1_init()
129 imx_check_clk_hws(hws, clk_data->num); in imx7ulp_clk_scg1_init()
133 CLK_OF_DECLARE(imx7ulp_clk_scg1, "fsl,imx7ulp-scg1", imx7ulp_clk_scg1_init);
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/serial/ |
| D | fsl-lpuart.txt | 4 - compatible :
5 - "fsl,vf610-lpuart" for lpuart compatible with the one integrated
6 on Vybrid vf610 SoC with 8-bit register organization
7 - "fsl,ls1021a-lpuart" for lpuart compatible with the one integrated
8 on LS1021A SoC with 32-bit big-endian register organization
9 - "fsl,imx7ulp-lpuart" for lpuart compatible with the one integrated
10 on i.MX7ULP SoC with 32-bit little-endian register organization
11 - reg : Address and length of the register set for the device
12 - interrupts : Should contain uart interrupt
13 - clocks : phandle + clock specifier pairs, one for each entry in clock-names
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-imx/ |
| D | pm-imx7ulp.c | 1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
39 /* system/bus clock enabled */ in imx7ulp_set_lpm()
43 /* system clock disabled, bus clock enabled */ in imx7ulp_set_lpm()
47 /* system/bus clock disabled */ in imx7ulp_set_lpm()
51 return -EINVAL; in imx7ulp_set_lpm()
63 np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-smc1"); in imx7ulp_pm_init()
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/fsl/ |
| D | mmdc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/mmdc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anson Huang <Anson.Huang@nxp.com>
15 - const: fsl,imx6q-mmdc
16 - items:
17 - enum:
18 - fsl,imx6qp-mmdc
19 - fsl,imx6sl-mmdc
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/gpio/ |
| D | gpio-vf610.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-vf610.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stefan Agner <stefan@agner.ch>
23 - const: fsl,vf610-gpio
24 - items:
25 - const: fsl,imx7ulp-gpio
26 - const: fsl,vf610-gpio
36 interrupt-controller: true
[all …]
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| /kernel/linux/linux-4.19/drivers/clocksource/ |
| D | timer-imx-tpm.c | 1 // SPDX-License-Identifier: GPL-2.0+
91 return clocksource_mmio_init(timer_base + TPM_CNT, "imx-tpm", in tpm_clocksource_init()
112 return (int)(next - now) <= 0 ? -ETIME : 0; in tpm_set_next_event()
135 evt->event_handler(evt); in tpm_timer_interrupt()
159 GENMASK(counter_width - 1, 1)); in tpm_clockevent_init()
173 return -ENXIO; in tpm_timer_init()
179 ret = -ENOENT; in tpm_timer_init()
187 ret = -ENODEV; in tpm_timer_init()
194 pr_err("tpm: ipg clock enable failed (%d)\n", ret); in tpm_timer_init()
200 pr_err("tpm: per clock enable failed (%d)\n", ret); in tpm_timer_init()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/ |
| D | fsl-sai.txt | 10 - compatible : Compatible list, contains "fsl,vf610-sai",
11 "fsl,imx6sx-sai", "fsl,imx6ul-sai",
12 "fsl,imx7ulp-sai", "fsl,imx8mq-sai" or
13 "fsl,imx8qm-sai".
15 - reg : Offset and length of the register set for the device.
17 - clocks : Must contain an entry for each entry in clock-names.
19 - clock-names : Must include the "bus" for register access and
20 "mclk1", "mclk2", "mclk3" for bit clock and frame
21 clock providing.
22 - dmas : Generic dma devicetree binding as described in
[all …]
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| /kernel/linux/linux-5.10/drivers/clocksource/ |
| D | timer-imx-tpm.c | 1 // SPDX-License-Identifier: GPL-2.0+
13 #include "timer-of.h"
99 return (int)(next - now) <= 0 ? -ETIME : 0; in tpm_set_next_event()
122 evt->event_handler(evt); in tpm_timer_interrupt()
159 "imx-tpm", in tpm_clocksource_init()
171 GENMASK(counter_width - 1, in tpm_clockevent_init()
183 return -ENODEV; in tpm_timer_init()
188 pr_err("tpm: ipg clock enable failed (%d)\n", ret); in tpm_timer_init()
201 /* use rating 200 for 32-bit counter and 150 for 16-bit counter */ in tpm_timer_init()
222 * div 8 for 32-bit counter and div 128 for 16-bit counter in tpm_timer_init()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/nvmem/ |
| D | imx-ocotp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/imx-ocotp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings
10 - Anson Huang <Anson.Huang@nxp.com>
13 This binding represents the on-chip eFuse OTP controller found on
18 - $ref: "nvmem.yaml#"
23 - items:
24 - enum:
[all …]
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