| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/powerpc/power8/ |
| D | frontend.json | 5 …"BriefDescription": "Branch instruction completed with a target address less than current instruct…
11 "BriefDescription": "Branch Instruction Finished",
23 "BriefDescription": "Branch Instruction completed",
71 …ption": "Initial and Final Pump Scope was chip pump (prediction=correct) for an instruction fetch",
72 …ope and data sourced across this scope was chip pump (prediction=correct) for an instruction fetch"
89 …Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different …
90 …Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different …
95 …Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different No…
96 …Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different No…
101 …: "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Gr…
[all …]
|
| D | other.json | 305 "BriefDescription": "Completion stall due to VSU scalar instruction",
311 "BriefDescription": "Completion stall due to VSU scalar long latency instruction",
323 "BriefDescription": "Completion stall due to VSU vector instruction",
329 "BriefDescription": "Completion stall due to VSU vector long instruction",
335 "BriefDescription": "Completion stall due to VSU instruction",
359 "BriefDescription": "IFU Finished a (non-branch) instruction",
713 "BriefDescription": "Dispatch/CLB Hold: Sync type instruction",
887 "BriefDescription": "Convert instruction executed",
893 "BriefDescription": "Estimate instruction executed",
899 "BriefDescription": "Round to single precision instruction executed",
[all …]
|
| /kernel/linux/linux-4.19/tools/perf/pmu-events/arch/powerpc/power8/ |
| D | frontend.json | 5 …"BriefDescription": "Branch instruction completed with a target address less than current instruct…
11 "BriefDescription": "Branch Instruction Finished",
23 "BriefDescription": "Branch Instruction completed",
71 …ption": "Initial and Final Pump Scope was chip pump (prediction=correct) for an instruction fetch",
72 …ope and data sourced across this scope was chip pump (prediction=correct) for an instruction fetch"
89 …Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different …
90 …Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different …
95 …Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different No…
96 …Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different No…
101 …: "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Gr…
[all …]
|
| D | other.json | 305 "BriefDescription": "Completion stall due to VSU scalar instruction",
311 "BriefDescription": "Completion stall due to VSU scalar long latency instruction",
323 "BriefDescription": "Completion stall due to VSU vector instruction",
329 "BriefDescription": "Completion stall due to VSU vector long instruction",
335 "BriefDescription": "Completion stall due to VSU instruction",
371 "BriefDescription": "IFU Finished a (non-branch) instruction",
725 "BriefDescription": "Dispatch/CLB Hold: Sync type instruction",
899 "BriefDescription": "Convert instruction executed",
905 "BriefDescription": "Estimate instruction executed",
911 "BriefDescription": "Round to single precision instruction executed",
[all …]
|
| /kernel/linux/linux-5.10/Documentation/virt/kvm/ |
| D | s390-pv.rst | 26 the behavior of the SIE instruction. A new format 4 state description
48 of an instruction emulation by KVM, e.g. we can never inject a
63 Instruction emulation
65 With the format 4 state description for PVMs, the SIE instruction already
67 to interpret every instruction, but needs to hand some tasks to KVM;
71 Instruction Data Area (SIDA), the Interception Parameters (IP) and the
73 the instruction data, such as I/O data structures, are filtered.
74 Instruction data is copied to and from the SIDA when needed. Guest
78 Only GR values needed to emulate an instruction will be copied into this
82 the bytes of the instruction text, but with pre-set register values
[all …]
|
| /kernel/linux/linux-4.19/arch/sh/kernel/ |
| D | traps_32.c | 82 * handle an instruction that does an unaligned memory access by emulating the
84 * - note that PC _may not_ point to the faulting instruction
85 * (if that instruction is in a branch delay slot)
88 static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs, in handle_unaligned_ins() argument
96 index = (instruction>>8)&15; /* 0x0F00 */ in handle_unaligned_ins()
99 index = (instruction>>4)&15; /* 0x00F0 */ in handle_unaligned_ins()
102 count = 1<<(instruction&3); in handle_unaligned_ins()
112 switch (instruction>>12) { in handle_unaligned_ins()
114 if (instruction & 8) { in handle_unaligned_ins()
146 dstu += (instruction&0x000F)<<2; in handle_unaligned_ins()
[all …]
|
| /kernel/linux/linux-5.10/arch/sh/kernel/ |
| D | traps_32.c | 79 * handle an instruction that does an unaligned memory access by emulating the
81 * - note that PC _may not_ point to the faulting instruction
82 * (if that instruction is in a branch delay slot)
85 static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs, in handle_unaligned_ins() argument
93 index = (instruction>>8)&15; /* 0x0F00 */ in handle_unaligned_ins()
96 index = (instruction>>4)&15; /* 0x00F0 */ in handle_unaligned_ins()
99 count = 1<<(instruction&3); in handle_unaligned_ins()
109 switch (instruction>>12) { in handle_unaligned_ins()
111 if (instruction & 8) { in handle_unaligned_ins()
143 dstu += (instruction&0x000F)<<2; in handle_unaligned_ins()
[all …]
|
| /kernel/linux/linux-4.19/arch/mips/include/asm/ |
| D | barrier.h | 15 * These values are used with the sync instruction to perform memory barriers.
16 * Types of ordering guarantees available through the SYNC instruction:
22 * specified instructions which are subsequent to the SYNC in the instruction
24 * instructions which are before the SYNC in the instruction stream.
25 * This potentially reduces how many cycles the barrier instruction must stall
34 * - Every synchronizable specified memory instruction (loads or stores or both)
35 * that occurs in the instruction stream before the SYNC instruction must be
40 * - The barrier does not guarantee the order in which instruction fetches are
46 * stores preceding the SYNC instruction and both loads and stores that are
47 * subsequent to the SYNC instruction. Non-zero values of stype may be defined
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/powerpc/power9/ |
| D | translation.json | 20 "BriefDescription": "Double-Precion or Quad-Precision instruction completed"
35 …chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request"
45 …"BriefDescription": "Finish stall due to a vector fixed point instruction in the execution pipelin…
50 "BriefDescription": "LSU Finished a PPC instruction (up to 4 per cycle)"
55 …: "Cycles during which the marked instruction is next to complete (completion is held up because t…
65 …"BriefDescription": "Completion stall due to a long latency vector fixed point instruction (divisi…
75 …ared or modified data from another core's L2/L3 on the same chip due to a instruction side request"
80 …": "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on …
100 …e TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request"
115 …"BriefDescription": "Finish stall because the NTF instruction was a vector instruction issued to t…
[all …]
|
| D | frontend.json | 5 …B with Modified (M) data from another core's L3 on the same chip due to a instruction side request"
15 …aded into the TLB from a location other than the local core's L3 due to a instruction side request"
20 …"BriefDescription": "The NTC instruction is being held at dispatch because there are no slots in t…
25 …instruction was a load or store that was held in LSAQ because an older instruction from SRQ or LRQ…
40 … or the original scope was System and it should have been smaller. Counts for an instruction fetch"
45 "BriefDescription": "Marked Instruction RC dispatched in L2"
60 … Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch"
70 …Finish stall because the NTF instruction was a store waiting for a slot in the store finish pipe. …
75 …s finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an ad…
80 …e. It takes 1 cycle for the ISU to process this request before the LSU instruction is allowed to c…
[all …]
|
| D | marked.json | 5 …"BriefDescription": "Number of cycles the marked instruction is experiencing a stall while it is n…
15 …"BriefDescription": "An instruction was marked. Includes both Random Instruction Sampling (RIS) at…
35 …cription": "The processor's Instruction cache was reloaded from local core's L2 with dispatch conf…
65 …"BriefDescription": "An instruction was marked at decode time. Random Instruction Sampling (RIS) o…
75 "BriefDescription": "Vector FP instruction completed"
80 …Description": "The processor's Instruction cache was reloaded from local core's L2 without conflic…
85 …ription": "The processor's Instruction cache was reloaded from a location other than the local cor…
90 …ch the NTC instruction is not allowed to complete because it was interrupted by ANY exception, whi…
115 … "BriefDescription": "Finish stall because the NTF instruction was awaiting L2 response for an SLB"
120 …: "The processor's Instruction cache was reloaded from another chip's memory on the same Node or G…
[all …]
|
| D | cache.json | 10 …"BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because any of…
15 …"BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (divisi…
20 …"BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution p…
35 …"BriefDescription": "Finish stall because the NTF instruction was a load that missed in the L1 and…
40 … processor's Instruction cache was reloaded either shared or modified data from another core's L2/…
45 …"BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its …
50 …n": "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Gro…
55 … Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node…
90 …"BriefDescription": "Finish stall because the NTF instruction was a load that hit on an older stor…
100 …Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Nod…
[all …]
|
| /kernel/linux/linux-4.19/tools/perf/pmu-events/arch/powerpc/power9/ |
| D | translation.json | 20 "BriefDescription": "Double-Precion or Quad-Precision instruction completed"
35 …chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request"
45 …"BriefDescription": "Finish stall due to a vector fixed point instruction in the execution pipelin…
50 "BriefDescription": "LSU Finished a PPC instruction (up to 4 per cycle)"
55 …: "Cycles during which the marked instruction is next to complete (completion is held up because t…
65 …"BriefDescription": "Completion stall due to a long latency vector fixed point instruction (divisi…
75 …ared or modified data from another core's L2/L3 on the same chip due to a instruction side request"
80 …": "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on …
100 …e TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request"
115 …"BriefDescription": "Finish stall because the NTF instruction was a vector instruction issued to t…
[all …]
|
| D | frontend.json | 5 …B with Modified (M) data from another core's L3 on the same chip due to a instruction side request"
15 …aded into the TLB from a location other than the local core's L3 due to a instruction side request"
20 …"BriefDescription": "The NTC instruction is being held at dispatch because there are no slots in t…
25 …instruction was a load or store that was held in LSAQ because an older instruction from SRQ or LRQ…
40 … or the original scope was System and it should have been smaller. Counts for an instruction fetch"
45 "BriefDescription": "Marked Instruction RC dispatched in L2"
60 … Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch"
70 …Finish stall because the NTF instruction was a store waiting for a slot in the store finish pipe. …
75 …s finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an ad…
80 …e. It takes 1 cycle for the ISU to process this request before the LSU instruction is allowed to c…
[all …]
|
| D | marked.json | 5 …"BriefDescription": "Number of cycles the marked instruction is experiencing a stall while it is n…
15 …"BriefDescription": "An instruction was marked. Includes both Random Instruction Sampling (RIS) at…
35 …cription": "The processor's Instruction cache was reloaded from local core's L2 with dispatch conf…
65 …"BriefDescription": "An instruction was marked at decode time. Random Instruction Sampling (RIS) o…
75 "BriefDescription": "Vector FP instruction completed"
80 …Description": "The processor's Instruction cache was reloaded from local core's L2 without conflic…
85 …ription": "The processor's Instruction cache was reloaded from a location other than the local cor…
90 …ch the NTC instruction is not allowed to complete because it was interrupted by ANY exception, whi…
115 … "BriefDescription": "Finish stall because the NTF instruction was awaiting L2 response for an SLB"
120 …: "The processor's Instruction cache was reloaded from another chip's memory on the same Node or G…
[all …]
|
| D | cache.json | 10 …"BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because any of…
15 …"BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (divisi…
20 …"BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution p…
35 …"BriefDescription": "Finish stall because the NTF instruction was a load that missed in the L1 and…
40 … processor's Instruction cache was reloaded either shared or modified data from another core's L2/…
45 …"BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its …
50 …n": "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Gro…
55 … Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node…
90 …"BriefDescription": "Finish stall because the NTF instruction was a load that hit on an older stor…
100 …Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Nod…
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/broadwellde/ |
| D | frontend.json | 5 "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
8 …instruction decoder queue is empty and can indicate that the application may be bound in the front…
15 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
18 …"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (…
25 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from M…
29 …n": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (I…
36 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe…
39 …"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (…
46 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from D…
50 …n": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (I…
[all …]
|
| /kernel/linux/linux-4.19/tools/perf/pmu-events/arch/x86/broadwellx/ |
| D | frontend.json | 5 "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
8 …instruction decoder queue is empty and can indicate that the application may be bound in the front…
15 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
18 …"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (…
25 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from M…
29 …n": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (I…
36 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe…
39 …"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (…
46 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from D…
50 …n": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (I…
[all …]
|
| /kernel/linux/linux-4.19/tools/perf/pmu-events/arch/x86/broadwell/ |
| D | frontend.json | 3 …instruction decoder queue is empty and can indicate that the application may be bound in the front…
9 "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
13 …"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (…
19 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
23 …n": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (I…
29 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from M…
34 …"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (…
40 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe…
44 …n": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (I…
50 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from D…
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/broadwellx/ |
| D | frontend.json | 5 "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
8 …instruction decoder queue is empty and can indicate that the application may be bound in the front…
15 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
18 …"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (…
25 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from M…
29 …n": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (I…
36 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe…
39 …"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (…
46 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from D…
50 …n": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (I…
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/broadwell/ |
| D | frontend.json | 3 …instruction decoder queue is empty and can indicate that the application may be bound in the front…
9 "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
13 …"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (…
19 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
23 …n": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (I…
29 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from M…
34 …"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (…
40 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe…
44 …n": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (I…
50 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from D…
[all …]
|
| /kernel/linux/linux-4.19/tools/perf/pmu-events/arch/x86/broadwellde/ |
| D | frontend.json | 5 "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
8 …instruction decoder queue is empty and can indicate that the application may be bound in the front…
15 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
18 …"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (…
25 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from M…
29 …n": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (I…
36 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe…
39 …"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (…
46 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from D…
50 …n": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (I…
[all …]
|
| /kernel/linux/linux-5.10/sound/soc/sof/xtensa/ |
| D | core.c | 24 * Instruction Set Architecture (ISA) Reference Manual
27 {0, "IllegalInstructionCause", "Illegal instruction"},
28 {1, "SyscallCause", "SYSCALL instruction"},
30 "Processor internal physical address or data error during instruction fetch"},
36 "MOVSP instruction, if caller’s registers are not in the register file"},
43 "PIF data error during instruction fetch"},
47 "PIF address error during instruction fetch"},
50 {16, "InstTLBMissCause", "Error during Instruction TLB refill"},
52 "Multiple instruction TLB entries matched"},
54 "An instruction fetch referenced a virtual address at a ring level less than CRING"},
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/silvermont/ |
| D | frontend.json | 3 …"PublicDescription": "This event counts all instruction fetches, not including most uncacheable\r\…
9 "BriefDescription": "Instruction fetches"
12 … "PublicDescription": "This event counts all instruction fetches from the instruction cache.",
18 "BriefDescription": "Instruction fetches from Icache"
21 … counts all instruction fetches that miss the Instruction cache or produce memory requests. This i…
30 …instruction is encountered by the front end of the machine. Other cases include when an instructi…
39 … times a decode restriction reduced the decode throughput due to wrong instruction length predicti…
45 … times a decode restriction reduced the decode throughput due to wrong instruction length predicti…
|
| /kernel/linux/linux-4.19/tools/perf/pmu-events/arch/x86/silvermont/ |
| D | frontend.json | 3 …"PublicDescription": "This event counts all instruction fetches, not including most uncacheable\r\…
9 "BriefDescription": "Instruction fetches"
12 … "PublicDescription": "This event counts all instruction fetches from the instruction cache.",
18 "BriefDescription": "Instruction fetches from Icache"
21 … counts all instruction fetches that miss the Instruction cache or produce memory requests. This i…
30 …instruction is encountered by the front end of the machine. Other cases include when an instructi…
39 … times a decode restriction reduced the decode throughput due to wrong instruction length predicti…
45 … times a decode restriction reduced the decode throughput due to wrong instruction length predicti…
|