| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/net/ |
| D | fsl-fec.txt | 40 1 "int0" 41 2 "int0", "pps" 42 3 "int0", "int1", "int2" 43 4 "int0", "int1", "int2", "pps" 46 tx/rx queues 1 and 2. "int0" will be used for queue 0 and ENET_MII interrupts. 47 For imx6sx, "int0" handles all 3 queues and ENET_MII. "pps" is for the pulse
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | fsl-fec.txt | 33 1 "int0" 34 2 "int0", "pps" 35 3 "int0", "int1", "int2" 36 4 "int0", "int1", "int2", "pps" 39 tx/rx queues 1 and 2. "int0" will be used for queue 0 and ENET_MII interrupts. 40 For imx6sx, "int0" handles all 3 queues and ENET_MII. "pps" is for the pulse
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | loongson,liointc.yaml | 40 - const: int0 83 interrupt-names = "int0", "int1"; 85 loongson,parent_int_map = <0xf0ffffff>, /* int0 */
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| /kernel/linux/linux-5.10/arch/mips/boot/dts/loongson/ |
| D | loongson64g-package.dtsi | 33 interrupt-names = "int0", "int1"; 35 loongson,parent_int_map = <0x00ffffff>, /* int0 */
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| D | loongson64c-package.dtsi | 36 interrupt-names = "int0", "int1"; 38 loongson,parent_int_map = <0xf0ffffff>, /* int0 */
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| D | loongson64v_4core_virtio.dts | 35 interrupt-names = "int0", "int1"; 37 loongson,parent_int_map = <0x00000001>, /* int0 */
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | stm32mp153.dtsi | 32 interrupt-names = "int0", "int1"; 45 interrupt-names = "int0", "int1";
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| D | dra76x.dtsi | 34 interrupt-names = "int0", "int1";
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/net/can/ |
| D | m_can.txt | 12 - interrupt-names : Should contain "int0" and "int1" 59 interrupt-names = "int0", "int1";
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/can/ |
| D | bosch,m_can.yaml | 37 - const: int0 132 interrupt-names = "int0", "int1";
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| /kernel/linux/linux-5.10/drivers/net/ethernet/amd/ |
| D | amd8111e.c | 537 /* Clear INT0 write 1 to clear register */ in amd8111e_init_hw_default() 538 reg_val = readl(mmio + INT0); in amd8111e_init_hw_default() 539 writel(reg_val, mmio + INT0); in amd8111e_init_hw_default() 588 * interrupts in INT0 597 /* Clear INT0 */ in amd8111e_disable_interrupt() 598 intr0 = readl(lp->mmio + INT0); in amd8111e_disable_interrupt() 599 writel(intr0, lp->mmio + INT0); in amd8111e_disable_interrupt() 602 readl(lp->mmio + INT0); in amd8111e_disable_interrupt() 1103 intr0 = readl(mmio + INT0); in amd8111e_interrupt() 1114 writel(intr0, mmio + INT0); in amd8111e_interrupt() [all …]
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| /kernel/linux/linux-4.19/drivers/net/ethernet/amd/ |
| D | amd8111e.c | 546 /* Clear INT0 write 1 to clear register */ in amd8111e_init_hw_default() 547 reg_val = readl(mmio + INT0); in amd8111e_init_hw_default() 548 writel(reg_val, mmio + INT0); in amd8111e_init_hw_default() 597 * interrupts in INT0 606 /* Clear INT0 */ in amd8111e_disable_interrupt() 607 intr0 = readl(lp->mmio + INT0); in amd8111e_disable_interrupt() 608 writel(intr0, lp->mmio + INT0); in amd8111e_disable_interrupt() 611 readl(lp->mmio + INT0); in amd8111e_disable_interrupt() 1111 intr0 = readl(mmio + INT0); in amd8111e_interrupt() 1122 writel(intr0, mmio + INT0); in amd8111e_interrupt() [all …]
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | dra76x.dtsi | 37 interrupt-names = "int0", "int1";
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| /kernel/linux/linux-5.10/drivers/net/can/sja1000/ |
| D | ems_pci.c | 50 #define PITA2_ICR_INT0 0x00000002 /* [RC] INT0 Active/Clear */ 51 #define PITA2_ICR_INT0_EN 0x00020000 /* [RW] Enable INT0 */
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| /kernel/linux/linux-4.19/drivers/net/can/sja1000/ |
| D | ems_pci.c | 61 #define PITA2_ICR_INT0 0x00000002 /* [RC] INT0 Active/Clear */ 62 #define PITA2_ICR_INT0_EN 0x00020000 /* [RW] Enable INT0 */
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| /kernel/linux/linux-4.19/arch/mips/include/asm/mach-loongson32/ |
| D | irq.h | 33 * INT0~3 Interrupt Numbers
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| /kernel/linux/linux-5.10/arch/mips/include/asm/mach-loongson32/ |
| D | irq.h | 29 * INT0~3 Interrupt Numbers
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| /kernel/linux/linux-4.19/drivers/staging/wilc1000/ |
| D | wilc_wlan.h | 147 /* 16: INT0 flag */ 167 /* 0: Clear INT0 */
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| /kernel/linux/linux-4.19/drivers/tty/serial/8250/ |
| D | 8250_exar.c | 456 * cleared by reading global INT0 or INT1 registers as interrupts are 465 /* Clear all PCI interrupts by reading INT0. No effect on IIR */ in exar_misc_handler() 468 /* Clear INT0 for Expansion Interface slave ports, too */ in exar_misc_handler()
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| /kernel/linux/linux-4.19/arch/m68k/mac/ |
| D | iop.c | 83 * Two sets of host interrupts are provided, INT0 and INT1. Both appear on one 85 * register. The IOP will raise INT0 when one or more messages in the send 563 /* INT0 indicates a state change on an outgoing message channel */ in iop_ism_irq()
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| /kernel/linux/linux-5.10/arch/m68k/mac/ |
| D | iop.c | 83 * Two sets of host interrupts are provided, INT0 and INT1. Both appear on one 85 * register. The IOP will raise INT0 when one or more messages in the send 567 /* INT0 indicates state change on an outgoing message channel */ in iop_ism_irq()
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| /kernel/linux/linux-4.19/arch/mips/loongson64/loongson-3/ |
| D | irq.c | 119 /* route HT1 int0 ~ int7 to cpu core0 INT1*/ in irq_router_init()
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| /kernel/linux/linux-5.10/arch/m68k/include/asm/ |
| D | MC68EZ328.h | 237 #define INT0_IRQ_NUM 8 /* External INT0 */ 263 #define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */ 292 #define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ 321 #define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ 427 #define PD_INT0 0x01 /* Use INT0 as PD[0] */
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| D | MC68328.h | 274 #define INT0_IRQ_NUM 8 /* External INT0 */ 305 #define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */ 339 #define IWR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ 369 #define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ 403 #define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
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| /kernel/linux/linux-4.19/arch/m68k/include/asm/ |
| D | MC68EZ328.h | 237 #define INT0_IRQ_NUM 8 /* External INT0 */ 263 #define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */ 292 #define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ 321 #define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ 427 #define PD_INT0 0x01 /* Use INT0 as PD[0] */
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