| /kernel/linux/linux-5.10/drivers/irqchip/ |
| D | irq-pruss-intc.c | 3 * PRU-ICSS INTC IRQChip driver for various TI SoCs
26 * INTC instance
85 * @num_system_events: number of input system events handled by the PRUSS INTC
87 * channels) supported by the PRUSS INTC
99 * @base: base virtual address of INTC register space
101 * @soc_config: cached PRUSS INTC IP configuration data
102 * @dev: PRUSS INTC device pointer
113 struct mutex lock; /* PRUSS INTC lock */
118 * @intc: PRUSS interrupt controller pointer
122 struct pruss_intc *intc; member
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| D | irq-bcm7038-l1.c | 83 static inline unsigned int reg_status(struct bcm7038_l1_chip *intc, in reg_status() argument
86 return (0 * intc->n_words + word) * sizeof(u32); in reg_status()
89 static inline unsigned int reg_mask_status(struct bcm7038_l1_chip *intc, in reg_mask_status() argument
92 return (1 * intc->n_words + word) * sizeof(u32); in reg_mask_status()
95 static inline unsigned int reg_mask_set(struct bcm7038_l1_chip *intc, in reg_mask_set() argument
98 return (2 * intc->n_words + word) * sizeof(u32); in reg_mask_set()
101 static inline unsigned int reg_mask_clr(struct bcm7038_l1_chip *intc, in reg_mask_clr() argument
104 return (3 * intc->n_words + word) * sizeof(u32); in reg_mask_clr()
125 struct bcm7038_l1_chip *intc = irq_desc_get_handler_data(desc); in bcm7038_l1_irq_handle() local
131 cpu = intc->cpus[cpu_logical_map(smp_processor_id())]; in bcm7038_l1_irq_handle()
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| D | irq-bcm6345-l1.c | 90 static inline unsigned int reg_enable(struct bcm6345_l1_chip *intc, in reg_enable() argument
94 return (1 * intc->n_words - word - 1) * sizeof(u32); in reg_enable()
96 return (0 * intc->n_words + word) * sizeof(u32); in reg_enable()
100 static inline unsigned int reg_status(struct bcm6345_l1_chip *intc, in reg_status() argument
104 return (2 * intc->n_words - word - 1) * sizeof(u32); in reg_status()
106 return (1 * intc->n_words + word) * sizeof(u32); in reg_status()
110 static inline unsigned int cpu_for_irq(struct bcm6345_l1_chip *intc, in cpu_for_irq() argument
113 return cpumask_first_and(&intc->cpumask, irq_data_get_affinity_mask(d)); in cpu_for_irq()
118 struct bcm6345_l1_chip *intc = irq_desc_get_handler_data(desc); in bcm6345_l1_irq_handle() local
124 cpu = intc->cpus[cpu_logical_map(smp_processor_id())]; in bcm6345_l1_irq_handle()
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| D | irq-ingenic.c | 36 struct ingenic_intc_data *intc = irq_get_handler_data(irq); in intc_cascade() local
37 struct irq_domain *domain = intc->domain; in intc_cascade()
42 for (i = 0; i < intc->num_chips; i++) { in intc_cascade()
64 struct ingenic_intc_data *intc; in ingenic_intc_of_init() local
71 intc = kzalloc(sizeof(*intc), GFP_KERNEL); in ingenic_intc_of_init()
72 if (!intc) { in ingenic_intc_of_init()
83 err = irq_set_handler_data(parent_irq, intc); in ingenic_intc_of_init()
87 intc->num_chips = num_chips; in ingenic_intc_of_init()
88 intc->base = of_iomap(node, 0); in ingenic_intc_of_init()
89 if (!intc->base) { in ingenic_intc_of_init()
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| /kernel/linux/linux-4.19/drivers/irqchip/ |
| D | irq-bcm6345-l1.c | 93 static inline unsigned int reg_enable(struct bcm6345_l1_chip *intc, in reg_enable() argument
97 return (1 * intc->n_words - word - 1) * sizeof(u32); in reg_enable()
99 return (0 * intc->n_words + word) * sizeof(u32); in reg_enable()
103 static inline unsigned int reg_status(struct bcm6345_l1_chip *intc, in reg_status() argument
107 return (2 * intc->n_words - word - 1) * sizeof(u32); in reg_status()
109 return (1 * intc->n_words + word) * sizeof(u32); in reg_status()
113 static inline unsigned int cpu_for_irq(struct bcm6345_l1_chip *intc, in cpu_for_irq() argument
116 return cpumask_first_and(&intc->cpumask, irq_data_get_affinity_mask(d)); in cpu_for_irq()
121 struct bcm6345_l1_chip *intc = irq_desc_get_handler_data(desc); in bcm6345_l1_irq_handle() local
127 cpu = intc->cpus[cpu_logical_map(smp_processor_id())]; in bcm6345_l1_irq_handle()
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| D | irq-bcm7038-l1.c | 77 static inline unsigned int reg_status(struct bcm7038_l1_chip *intc, in reg_status() argument
80 return (0 * intc->n_words + word) * sizeof(u32); in reg_status()
83 static inline unsigned int reg_mask_status(struct bcm7038_l1_chip *intc, in reg_mask_status() argument
86 return (1 * intc->n_words + word) * sizeof(u32); in reg_mask_status()
89 static inline unsigned int reg_mask_set(struct bcm7038_l1_chip *intc, in reg_mask_set() argument
92 return (2 * intc->n_words + word) * sizeof(u32); in reg_mask_set()
95 static inline unsigned int reg_mask_clr(struct bcm7038_l1_chip *intc, in reg_mask_clr() argument
98 return (3 * intc->n_words + word) * sizeof(u32); in reg_mask_clr()
119 struct bcm7038_l1_chip *intc = irq_desc_get_handler_data(desc); in bcm7038_l1_irq_handle() local
125 cpu = intc->cpus[cpu_logical_map(smp_processor_id())]; in bcm7038_l1_irq_handle()
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| D | irq-ingenic.c | 46 struct ingenic_intc_data *intc = irq_get_handler_data(irq); in intc_cascade() local
50 for (i = 0; i < intc->num_chips; i++) { in intc_cascade()
51 irq_reg = readl(intc->base + (i * CHIP_SIZE) + in intc_cascade()
84 .name = "SoC intc cascade interrupt",
90 struct ingenic_intc_data *intc; in ingenic_intc_of_init() local
97 intc = kzalloc(sizeof(*intc), GFP_KERNEL); in ingenic_intc_of_init()
98 if (!intc) { in ingenic_intc_of_init()
109 err = irq_set_handler_data(parent_irq, intc); in ingenic_intc_of_init()
113 intc->num_chips = num_chips; in ingenic_intc_of_init()
114 intc->base = of_iomap(node, 0); in ingenic_intc_of_init()
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/interrupt-controller/ |
| D | mrvl,intc.txt | 4 - compatible : Should be "mrvl,mmp-intc", "mrvl,mmp2-intc" or
5 "mrvl,mmp2-mux-intc"
7 If the interrupt controller is intc, address and length means the range
8 of the whold interrupt controller. If the interrupt controller is mux-intc,
9 address and length means one register. Since address of mux-intc is in the
10 range of intc. mux-intc is secondary interrupt controller.
12 only required in mux-intc interrupt controller.
14 only required in mux-intc interrupt controller.
18 - mrvl,intc-nr-irqs : Specifies the number of interrupts in the interrupt
24 intc: interrupt-controller@d4282000 {
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| D | ti,omap-intc-irq.txt | 1 Omap2/3 intc controller
3 On TI omap2 and 3 the intc interrupt controller can provide
8 "ti,omap2-intc"
9 "ti,omap3-intc"
10 "ti,dm814-intc"
11 "ti,dm816-intc"
12 "ti,am33xx-intc"
16 source, should be 1 for intc
23 intc: interrupt-controller@48200000 {
24 compatible = "ti,omap3-intc";
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | arm-realview-pba8.dts | 45 interrupt-parent = <&intc>;
51 intc: interrupt-controller@1e000000 { label
62 interrupt-parent = <&intc>;
67 interrupt-parent = <&intc>;
80 interrupt-parent = <&intc>;
85 interrupt-parent = <&intc>;
90 interrupt-parent = <&intc>;
95 interrupt-parent = <&intc>;
100 interrupt-parent = <&intc>;
105 interrupt-parent = <&intc>;
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| D | arm-realview-pbx-a9.dts | 89 interrupt-parent = <&intc>;
96 interrupt-parent = <&intc>;
102 interrupt-parent = <&intc>;
109 intc: interrupt-controller@1f000000 { label
120 interrupt-parent = <&intc>;
125 interrupt-parent = <&intc>;
130 interrupt-parent = <&intc>;
135 interrupt-parent = <&intc>;
140 interrupt-parent = <&intc>;
145 interrupt-parent = <&intc>;
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| D | arm-realview-eb.dts | 51 intc: interrupt-controller@10040000 { label
68 interrupt-parent = <&intc>;
73 interrupt-parent = <&intc>;
78 interrupt-parent = <&intc>;
83 interrupt-parent = <&intc>;
89 interrupt-parent = <&intc>;
94 interrupt-parent = <&intc>;
99 interrupt-parent = <&intc>;
104 interrupt-parent = <&intc>;
109 interrupt-parent = <&intc>;
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | arm-realview-pba8.dts | 45 interrupt-parent = <&intc>;
51 intc: interrupt-controller@1e000000 { label
62 interrupt-parent = <&intc>;
67 interrupt-parent = <&intc>;
80 interrupt-parent = <&intc>;
85 interrupt-parent = <&intc>;
90 interrupt-parent = <&intc>;
95 interrupt-parent = <&intc>;
100 interrupt-parent = <&intc>;
105 interrupt-parent = <&intc>;
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| D | arm-realview-pbx-a9.dts | 89 interrupt-parent = <&intc>;
96 interrupt-parent = <&intc>;
102 interrupt-parent = <&intc>;
109 intc: interrupt-controller@1f000000 { label
120 interrupt-parent = <&intc>;
125 interrupt-parent = <&intc>;
130 interrupt-parent = <&intc>;
135 interrupt-parent = <&intc>;
140 interrupt-parent = <&intc>;
145 interrupt-parent = <&intc>;
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| D | arm-realview-eb.dts | 51 intc: interrupt-controller@10040000 { label
68 interrupt-parent = <&intc>;
73 interrupt-parent = <&intc>;
78 interrupt-parent = <&intc>;
83 interrupt-parent = <&intc>;
89 interrupt-parent = <&intc>;
94 interrupt-parent = <&intc>;
99 interrupt-parent = <&intc>;
104 interrupt-parent = <&intc>;
109 interrupt-parent = <&intc>;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | mrvl,intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/mrvl,intc.yaml#
21 const: marvell,orion-intc
24 - mrvl,intc-nr-irqs
30 - mrvl,mmp-intc
31 - mrvl,mmp2-intc
41 - marvell,mmp3-intc
42 - mrvl,mmp2-mux-intc
51 const: mrvl,mmp2-mux-intc
72 - mrvl,mmp-intc
73 - mrvl,mmp2-intc
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| D | ingenic,intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/ingenic,intc.yaml#
19 - ingenic,jz4740-intc
20 - ingenic,jz4760-intc
21 - ingenic,jz4780-intc
24 - ingenic,jz4775-intc
25 - ingenic,jz4770-intc
26 - const: ingenic,jz4760-intc
28 - const: ingenic,x1000-intc
29 - const: ingenic,jz4780-intc
31 - const: ingenic,jz4725b-intc
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| D | csky,apb-intc.txt | 8 - csky,apb-intc is used in a lot of csky fpgas and socs, it support 64 irq nums.
9 - csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported.
10 - csky,gx6605s-intc is gx6605s soc internal irq interrupt controller, 64 irq nums.
13 intc node bindings definition
23 Definition: must be "csky,apb-intc"
24 "csky,dual-apb-intc"
25 "csky,gx6605s-intc"
43 intc: interrupt-controller@500000 {
44 compatible = "csky,apb-intc";
50 intc: interrupt-controller@500000 {
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| D | ti,omap-intc-irq.txt | 1 Omap2/3 intc controller
3 On TI omap2 and 3 the intc interrupt controller can provide
8 "ti,omap2-intc"
9 "ti,omap3-intc"
10 "ti,dm814-intc"
11 "ti,dm816-intc"
12 "ti,am33xx-intc"
16 source, should be 1 for intc
23 intc: interrupt-controller@48200000 {
24 compatible = "ti,omap3-intc";
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| D | amlogic,meson-gpio-intc.txt | 12 - compatible : must have "amlogic,meson8-gpio-intc" and either
13 "amlogic,meson8-gpio-intc" for meson8 SoCs (S802) or
14 "amlogic,meson8b-gpio-intc" for meson8b SoCs (S805) or
15 "amlogic,meson-gxbb-gpio-intc" for GXBB SoCs (S905) or
16 "amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912)
17 "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X)
18 "amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2)
19 "amlogic,meson-sm1-gpio-intc" for SM1 SoCs (S905D3, S905X3, S905Y3)
20 "amlogic,meson-a1-gpio-intc" for A1 SoCs (A113L)
31 compatible = "amlogic,meson-gxbb-gpio-intc",
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| /kernel/linux/linux-5.10/arch/mips/pci/ |
| D | fixup-sni.c | 26 #define INTC PCIMT_IRQ_INTC macro
44 /* INTA INTB INTC INTD */
50 { 0, INTB, INTC, INTD, INTA }, /* Slot 2 */
51 { 0, INTC, INTD, INTA, INTB }, /* Slot 3 */
52 { 0, INTD, INTA, INTB, INTC }, /* Slot 4 */
61 /* INTA INTB INTC INTD */
64 { 0, INTC, INTD, INTA, INTB }, /* Slot 1 */
67 { 0, INTB, INTC, INTD, INTA }, /* Slot 2 */
68 { 0, INTC, INTD, INTA, INTB }, /* Slot 3 */
69 { 0, INTD, INTA, INTB, INTC }, /* Slot 4 */
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| /kernel/linux/linux-4.19/arch/mips/pci/ |
| D | fixup-sni.c | 26 #define INTC PCIMT_IRQ_INTC macro
44 /* INTA INTB INTC INTD */
50 { 0, INTB, INTC, INTD, INTA }, /* Slot 2 */
51 { 0, INTC, INTD, INTA, INTB }, /* Slot 3 */
52 { 0, INTD, INTA, INTB, INTC }, /* Slot 4 */
61 /* INTA INTB INTC INTD */
64 { 0, INTC, INTD, INTA, INTB }, /* Slot 1 */
67 { 0, INTB, INTC, INTD, INTA }, /* Slot 2 */
68 { 0, INTC, INTD, INTA, INTB }, /* Slot 3 */
69 { 0, INTD, INTA, INTB, INTC }, /* Slot 4 */
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| /kernel/linux/linux-4.19/arch/m68k/coldfire/ |
| D | Makefile | 19 obj-$(CONFIG_M5206) += m5206.o timers.o intc.o reset.o
20 obj-$(CONFIG_M5206e) += m5206.o timers.o intc.o reset.o
21 obj-$(CONFIG_M520x) += m520x.o pit.o intc-simr.o reset.o
22 obj-$(CONFIG_M523x) += m523x.o pit.o dma_timer.o intc-2.o reset.o
23 obj-$(CONFIG_M5249) += m5249.o timers.o intc.o intc-5249.o reset.o
24 obj-$(CONFIG_M525x) += m525x.o timers.o intc.o intc-525x.o reset.o
25 obj-$(CONFIG_M527x) += m527x.o pit.o intc-2.o reset.o
26 obj-$(CONFIG_M5272) += m5272.o intc-5272.o timers.o
27 obj-$(CONFIG_M528x) += m528x.o pit.o intc-2.o reset.o
28 obj-$(CONFIG_M5307) += m5307.o timers.o intc.o reset.o
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| /kernel/linux/linux-5.10/arch/m68k/coldfire/ |
| D | Makefile | 19 obj-$(CONFIG_M5206) += m5206.o timers.o intc.o reset.o
20 obj-$(CONFIG_M5206e) += m5206.o timers.o intc.o reset.o
21 obj-$(CONFIG_M520x) += m520x.o pit.o intc-simr.o reset.o
22 obj-$(CONFIG_M523x) += m523x.o pit.o dma_timer.o intc-2.o reset.o
23 obj-$(CONFIG_M5249) += m5249.o timers.o intc.o intc-5249.o reset.o
24 obj-$(CONFIG_M525x) += m525x.o timers.o intc.o intc-525x.o reset.o
25 obj-$(CONFIG_M527x) += m527x.o pit.o intc-2.o reset.o
26 obj-$(CONFIG_M5272) += m5272.o intc-5272.o timers.o
27 obj-$(CONFIG_M528x) += m528x.o pit.o intc-2.o reset.o
28 obj-$(CONFIG_M5307) += m5307.o timers.o intc.o reset.o
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| /kernel/linux/linux-4.19/arch/sh/include/mach-common/mach/ |
| D | microdev.h | 19 * controller (INTC) on the CPU-board FPGA. should be noted that there
20 * is an INTC on the FPGA, and a separate INTC on the SH4-202 core -
25 #define MICRODEV_FPGA_INTC_BASE 0xa6110000ul /* INTC base address on CPU-board FPGA */
26 …INTENB_REG (MICRODEV_FPGA_INTC_BASE+0ul) /* Interrupt Enable Register on INTC on CPU-board FPGA */
27 …NTDSB_REG (MICRODEV_FPGA_INTC_BASE+8ul) /* Interrupt Disable Register on INTC on CPU-board FPGA */
28 #define MICRODEV_FPGA_INTC_MASK(n) (1ul<<(n)) /* Interrupt mask to enable/disable INTC in CPU-bo…
29 …(MICRODEV_FPGA_INTC_BASE+0x10+((n)/8)*8)/* Interrupt Priority Register on INTC on CPU-board FPGA */
31 …(n) (MICRODEV_FPGA_INTPRI_LEVEL((n),0xful)) /* Interrupt Priority Mask on INTC on CPU-board FPGA */
32 …TSRC_REG (MICRODEV_FPGA_INTC_BASE+0x30ul) /* Interrupt Source Register on INTC on CPU-board FPGA */
33 …REQ_REG (MICRODEV_FPGA_INTC_BASE+0x38ul) /* Interrupt Request Register on INTC on CPU-board FPGA */
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