| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | mstar,mst-intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mstar,mst-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark-PK Tsai <mark-pk.tsai@mediatek.com>
21 const: mstar,mst-intc
23 interrupt-controller: true
25 "#interrupt-cells":
33 mstar,irqs-map-range:
35 The range <start, end> of parent interrupt controller's interrupt
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| /kernel/linux/linux-4.19/Documentation/ |
| D | IRQ-domain.txt | 9 that each one gets assigned non-overlapping allocations of Linux
24 For this reason we need a mechanism to separate controller-local
29 the controller-local IRQ (hwirq) number into the Linux IRQ number
55 the hwirq, and call the .map() callback so the driver can perform any
67 callbacks) then it can be directly obtained from irq_data->hwirq.
74 Which reverse map type should be used depends on the use case. Each
75 of the reverse map types are described below:
78 ------
85 The linear reverse map maintains a fixed size table indexed by the
89 The Linear map is a good choice when the maximum number of hwirqs is
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| /kernel/linux/linux-5.10/Documentation/core-api/irq/ |
| D | irq-domain.rst | 9 that each one gets assigned non-overlapping allocations of Linux
24 For this reason we need a mechanism to separate controller-local
29 the controller-local IRQ (hwirq) number into the Linux IRQ number
55 the hwirq, and call the .map() callback so the driver can perform any
67 callbacks) then it can be directly obtained from irq_data->hwirq.
74 Which reverse map type should be used depends on the use case. Each
75 of the reverse map types are described below:
78 ------
85 The linear reverse map maintains a fixed size table indexed by the
89 The Linear map is a good choice when the maximum number of hwirqs is
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| /kernel/linux/linux-4.19/arch/sparc/kernel/ |
| D | of_device_64.c | 1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/dma-mapping.h>
20 unsigned long ret = res->start + offset; in of_ioremap()
23 if (res->flags & IORESOURCE_MEM) in of_ioremap()
36 if (res->flags & IORESOURCE_MEM) in of_iounmap()
49 if (!strcmp(np->name, "pci")) { in of_bus_pci_match()
58 * parent as-is, not with the PCI translate in of_bus_pci_match()
80 if (!strcmp(np->name, "pci")) { in of_bus_simba_match()
88 static int of_bus_simba_map(u32 *addr, const u32 *range, in of_bus_simba_map() argument
103 static int of_bus_pci_map(u32 *addr, const u32 *range, in of_bus_pci_map() argument
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| D | of_device_32.c | 1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/dma-mapping.h>
25 if (!strcmp(np->type, "pci") || !strcmp(np->type, "pciex")) { in of_bus_pci_match()
29 * parent as-is, not with the PCI translate in of_bus_pci_match()
50 static int of_bus_pci_map(u32 *addr, const u32 *range, in of_bus_pci_map() argument
57 if ((addr[0] ^ range[0]) & 0x03000000) in of_bus_pci_map()
58 return -EINVAL; in of_bus_pci_map()
60 if (of_out_of_range(addr + 1, range + 1, range + na + pna, in of_bus_pci_map()
61 na - 1, ns)) in of_bus_pci_map()
62 return -EINVAL; in of_bus_pci_map()
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| /kernel/linux/linux-5.10/arch/sparc/kernel/ |
| D | of_device_64.c | 1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/dma-mapping.h>
20 unsigned long ret = res->start + offset; in of_ioremap()
23 if (res->flags & IORESOURCE_MEM) in of_ioremap()
36 if (res->flags & IORESOURCE_MEM) in of_iounmap()
58 * parent as-is, not with the PCI translate in of_bus_pci_match()
88 static int of_bus_simba_map(u32 *addr, const u32 *range, in of_bus_simba_map() argument
103 static int of_bus_pci_map(u32 *addr, const u32 *range, in of_bus_pci_map() argument
110 if (!((addr[0] ^ range[0]) & 0x03000000)) in of_bus_pci_map()
113 /* Special exception, we can map a 64-bit address into in of_bus_pci_map()
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| D | of_device_32.c | 1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/dma-mapping.h>
29 * parent as-is, not with the PCI translate in of_bus_pci_match()
50 static int of_bus_pci_map(u32 *addr, const u32 *range, in of_bus_pci_map() argument
57 if ((addr[0] ^ range[0]) & 0x03000000) in of_bus_pci_map()
58 return -EINVAL; in of_bus_pci_map()
60 if (of_out_of_range(addr + 1, range + 1, range + na + pna, in of_bus_pci_map()
61 na - 1, ns)) in of_bus_pci_map()
62 return -EINVAL; in of_bus_pci_map()
64 /* Start with the parent range base. */ in of_bus_pci_map()
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | mstar-v7.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a7";
27 compatible = "arm,armv7-timer";
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| /kernel/linux/linux-4.19/include/linux/gpio/ |
| D | driver.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
12 #include <linux/pinctrl/pinconf-generic.h>
25 * struct gpio_irq_chip - GPIO interrupt controller
54 * GPIO IRQs, provided by GPIO driver.
113 * @map:
117 unsigned int *map; member
145 * will allocate and map all IRQs during initialization.
157 * struct gpio_chip - abstract a GPIO controller
159 * number or the name of the SoC IP-block implementing it.
163 * @request: optional hook for chip-specific activation, such as
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| /kernel/linux/linux-5.10/drivers/soc/ti/ |
| D | knav_qmss_queue.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/dma-mapping.h>
42 * are to be re-defined
55 (kdev->instances + (idx << kdev->inst_shift))
58 list_for_each_entry_rcu(qh, &inst->handles, list, \
62 for (idx = 0, inst = kdev->instances; \
63 idx < (kdev)->num_queues_in_use; \
93 if (atomic_read(&qh->notifier_enabled) <= 0) in knav_queue_notify()
95 if (WARN_ON(!qh->notifier_fn)) in knav_queue_notify()
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| /kernel/linux/linux-4.19/drivers/soc/ti/ |
| D | knav_qmss_queue.c | 4 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
20 #include <linux/dma-mapping.h>
48 * are to be re-defined
61 (kdev->instances + (idx << kdev->inst_shift))
64 list_for_each_entry_rcu(qh, &inst->handles, list)
67 for (idx = 0, inst = kdev->instances; \
68 idx < (kdev)->num_queues_in_use; \
98 if (atomic_read(&qh->notifier_enabled) <= 0) in knav_queue_notify()
100 if (WARN_ON(!qh->notifier_fn)) in knav_queue_notify()
102 this_cpu_inc(qh->stats->notifies); in knav_queue_notify()
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| /kernel/linux/linux-5.10/include/linux/gpio/ |
| D | driver.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
12 #include <linux/pinctrl/pinconf-generic.h>
29 * struct gpio_irq_chip - GPIO interrupt controller
66 * If non-NULL, will be set as the parent of this GPIO interrupt
78 * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the
85 * If some ranges of hardware IRQs do not have a corresponding parent
86 * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and
101 * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell
135 * GPIO IRQs, provided by GPIO driver.
193 * @map:
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| /kernel/linux/linux-4.19/kernel/irq/ |
| D | irqdomain.c | 1 // SPDX-License-Identifier: GPL-2.0
49 * irq_domain_alloc_fwnode - Allocate a fwnode_handle suitable for
54 * @data: Optional user-provided data
77 n = kasprintf(GFP_KERNEL, "%s-%d", name, id); in __irq_domain_alloc_fwnode()
90 fwid->type = type; in __irq_domain_alloc_fwnode()
91 fwid->name = n; in __irq_domain_alloc_fwnode()
92 fwid->data = data; in __irq_domain_alloc_fwnode()
93 fwid->fwnode.ops = &irqchip_fwnode_ops; in __irq_domain_alloc_fwnode()
94 return &fwid->fwnode; in __irq_domain_alloc_fwnode()
99 * irq_domain_free_fwnode - Free a non-OF-backed fwnode_handle
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| /kernel/linux/linux-5.10/drivers/irqchip/ |
| D | irq-mst-intc.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
4 * Author Mark-PK Tsai <mark-pk.tsai@mediatek.com>
37 raw_spin_lock_irqsave(&cd->lock, flags); in mst_set_irq()
38 val = readw_relaxed(cd->base + offset) | mask; in mst_set_irq()
39 writew_relaxed(val, cd->base + offset); in mst_set_irq()
40 raw_spin_unlock_irqrestore(&cd->lock, flags); in mst_set_irq()
53 raw_spin_lock_irqsave(&cd->lock, flags); in mst_clear_irq()
54 val = readw_relaxed(cd->base + offset) & ~mask; in mst_clear_irq()
55 writew_relaxed(val, cd->base + offset); in mst_clear_irq()
56 raw_spin_unlock_irqrestore(&cd->lock, flags); in mst_clear_irq()
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| D | irq-ti-sci-inta.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
24 #include <asm-generic/msi.h>
44 * struct ti_sci_inta_event_desc - Description of an event coming to
59 * struct ti_sci_inta_vint_desc - Description of a virtual interrupt coming out
78 * struct ti_sci_inta_irq_domain - Structure representing a TISCI based
87 * @ti_sci_id: TI-SCI device identifier
89 * @unmapped_dev_ids: Pointer to an array of TI-SCI device identifiers of
91 * Unmapped Events are not part of the Global Event Map and
95 * generating Unmapped Event, we must use the INTA's TI-SCI
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| /kernel/linux/linux-5.10/kernel/irq/ |
| D | irqdomain.c | 1 // SPDX-License-Identifier: GPL-2.0
49 * __irq_domain_alloc_fwnode - Allocate a fwnode_handle suitable for
54 * @pa: Optional user-provided physical address
78 n = kasprintf(GFP_KERNEL, "%s-%d", name, id); in __irq_domain_alloc_fwnode()
91 fwid->type = type; in __irq_domain_alloc_fwnode()
92 fwid->name = n; in __irq_domain_alloc_fwnode()
93 fwid->pa = pa; in __irq_domain_alloc_fwnode()
94 fwid->fwnode.ops = &irqchip_fwnode_ops; in __irq_domain_alloc_fwnode()
95 return &fwid->fwnode; in __irq_domain_alloc_fwnode()
100 * irq_domain_free_fwnode - Free a non-OF-backed fwnode_handle
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| /kernel/linux/linux-4.19/drivers/pinctrl/ |
| D | pinctrl-ocelot.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * Author: <alexandre.belloni@free-electrons.com>
19 #include <linux/pinctrl/pinconf-generic.h>
120 struct regmap *map; member
204 *groups = info->func[function].groups; in ocelot_get_function_groups()
205 *num_groups = info->func[function].ngroups; in ocelot_get_function_groups()
216 if (function == p->functions[i]) in ocelot_pin_function_idx()
220 return -1; in ocelot_pin_function_idx()
232 return -EINVAL; in ocelot_pinmux_set_mux()
241 regmap_update_bits(info->map, OCELOT_GPIO_ALT0, BIT(pin->pin), in ocelot_pinmux_set_mux()
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| D | pinctrl-single.c | 29 #include <linux/pinctrl/pinconf-generic.h>
31 #include <linux/platform_data/pinctrl-single.h>
38 #define DRIVER_NAME "pinctrl-single"
42 * struct pcs_func_vals - mux function register offset and value pair
53 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
70 * struct pcs_conf_type - pinconf property name, pinconf param pair
80 * struct pcs_function - pinctrl function
100 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
114 * struct pcs_data - wrapper for data needed by pinctrl framework
128 * struct pcs_soc_data - SoC specific settings
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| /kernel/linux/linux-5.10/arch/mips/ralink/ |
| D | irq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
29 /* we have a cascade of 8 irqs */
32 /* we have 32 SoC irqs */
71 rt_intc_w32(BIT(d->hwirq), INTC_REG_ENABLE); in ralink_intc_irq_unmask()
76 rt_intc_w32(BIT(d->hwirq), INTC_REG_DISABLE); in ralink_intc_irq_mask()
143 .map = intc_map,
153 if (!of_property_read_u32_array(node, "ralink,intc-registers", in intc_of_init()
155 pr_info("intc: using register map from devicetree\n"); in intc_of_init()
162 panic("Failed to get intc memory range"); in intc_of_init()
195 { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init },
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| /kernel/linux/linux-4.19/arch/mips/ralink/ |
| D | irq.c | 31 /* we have a cascade of 8 irqs */
34 /* we have 32 SoC irqs */
73 rt_intc_w32(BIT(d->hwirq), INTC_REG_ENABLE); in ralink_intc_irq_unmask()
78 rt_intc_w32(BIT(d->hwirq), INTC_REG_DISABLE); in ralink_intc_irq_mask()
145 .map = intc_map,
155 if (!of_property_read_u32_array(node, "ralink,intc-registers", in intc_of_init()
157 pr_info("intc: using register map from devicetree\n"); in intc_of_init()
164 panic("Failed to get intc memory range"); in intc_of_init()
197 { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init },
198 { .compatible = "ralink,rt2880-intc", .data = intc_of_init },
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| /kernel/linux/linux-5.10/drivers/pinctrl/ |
| D | pinctrl-single.c | 29 #include <linux/pinctrl/pinconf-generic.h>
31 #include <linux/platform_data/pinctrl-single.h>
38 #define DRIVER_NAME "pinctrl-single"
42 * struct pcs_func_vals - mux function register offset and value pair
54 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
71 * struct pcs_conf_type - pinconf property name, pinconf param pair
81 * struct pcs_function - pinctrl function
103 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
117 * struct pcs_data - wrapper for data needed by pinctrl framework
131 * struct pcs_soc_data - SoC specific settings
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| /kernel/linux/linux-4.19/arch/powerpc/platforms/52xx/ |
| D | mpc52xx_pic.c | 23 * -----------------
26 * group has 3 irqs, External IRQ0, slice timer 0 irq, and wake from deep
27 * sleep. Main group include the other 3 external IRQs, slice timer 1, RTC,
29 * remaining irq sources from all of the on-chip peripherals (PSCs, Ethernet,
33 * -----
39 * a unique range of the global IRQ# space.
41 * To define a range of virq numbers for this controller, this driver first
61 * -------------------
62 * For actually manipulating IRQs (masking, enabling, clearing, etc) this
74 * register even though one of the external IRQs is in the critical group and
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| /kernel/linux/linux-5.10/arch/powerpc/platforms/52xx/ |
| D | mpc52xx_pic.c | 23 * -----------------
26 * group has 3 irqs, External IRQ0, slice timer 0 irq, and wake from deep
27 * sleep. Main group include the other 3 external IRQs, slice timer 1, RTC,
29 * remaining irq sources from all of the on-chip peripherals (PSCs, Ethernet,
33 * -----
39 * a unique range of the global IRQ# space.
41 * To define a range of virq numbers for this controller, this driver first
61 * -------------------
62 * For actually manipulating IRQs (masking, enabling, clearing, etc) this
74 * register even though one of the external IRQs is in the critical group and
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| /kernel/linux/linux-4.19/include/linux/ |
| D | regmap.h | 5 * Register map access API
47 * struct reg_default - Default value for a register.
61 * struct reg_sequence - An individual write from a sequence of writes.
76 #define regmap_update_bits(map, reg, mask, val) \ argument
77 regmap_update_bits_base(map, reg, mask, val, NULL, false, false)
78 #define regmap_update_bits_async(map, reg, mask, val)\ argument
79 regmap_update_bits_base(map, reg, mask, val, NULL, true, false)
80 #define regmap_update_bits_check(map, reg, mask, val, change)\ argument
81 regmap_update_bits_base(map, reg, mask, val, change, false, false)
82 #define regmap_update_bits_check_async(map, reg, mask, val, change)\ argument
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| /kernel/linux/linux-4.19/arch/mips/lantiq/ |
| D | irq.c | 24 /* register definitions - internal irqs */
31 #define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)
33 /* register definitions - external irqs */
46 * irqs generated by devices attached to the EBU need to be acked in
61 /* we have a cascade of 8 irqs */
75 return -1; in ltq_eiu_get_irq()
81 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; in ltq_disable_irq()
92 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; in ltq_mask_and_ack_irq()
103 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; in ltq_ack_irq()
113 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; in ltq_enable_irq()
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