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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dqca,ar803x.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
18 - $ref: ethernet-phy.yaml#
21 qca,clk-out-frequency:
26 qca,clk-out-strength:
31 qca,keep-pll-enabled:
[all …]
/kernel/linux/linux-5.10/drivers/clk/meson/
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0
11 * In the most basic form, a Meson PLL is composed as follows:
13 * PLL
14 * +--------------------------------+
16 * | +--+ |
17 * in >>-----[ /N ]--->| | +-----+ |
18 * | | |------| DCO |---->> out
19 * | +--------->| | +--v--+ |
20 * | | +--+ | |
22 * | +--[ *(M + (F/Fmax) ]<--+ |
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dfsl-ls1028a-kontron-sl28-var4.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board.
12 /dts-v1/;
13 #include "fsl-ls1028a-kontron-sl28.dts"
14 #include <dt-bindings/net/qca-ar803x.h>
17 model = "Kontron SMARC-sAL28 (Dual PHY)";
18 compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a";
22 phy-handle = <&phy1>;
23 phy-connection-type = "rgmii-id";
27 #address-cells = <1>;
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/bridge/
Dtc358768.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com
26 /* Global (16-bit addressable) */
43 /* Debug (16-bit addressable) */
49 /* TX PHY (32-bit addressable) */
61 /* TX PPI (32-bit addressable) */
77 /* TX CTRL (32-bit addressable) */
98 /* DSITX CTRL (16-bit addressable) */
141 int enabled; member
151 /* Parameters for PLL programming */
[all …]
/kernel/linux/linux-5.10/drivers/net/phy/
Dat803x.c1 // SPDX-License-Identifier: GPL-2.0+
22 #include <dt-bindings/net/qca-ar803x.h>
86 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
99 /* AT803x supports either the XTAL input pad, an internal PLL or the
101 * is only used for 25 MHz output, all other frequencies need the PLL.
105 * By default the PLL is only enabled if there is a link. Otherwise
106 * the PHY will go into low power state and disabled the PLL. You can
107 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always
108 * enabled.
122 * but doesn't support choosing between XTAL/PLL and DSP.
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/radeon/
Dradeon_legacy_crtc.c2 * Copyright 2007-8 Advanced Micro Devices, Inc.
37 struct drm_device *dev = crtc->dev; in radeon_overscan_setup()
38 struct radeon_device *rdev = dev->dev_private; in radeon_overscan_setup()
41 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
42 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
43 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
49 struct drm_device *dev = crtc->dev; in radeon_legacy_rmx_mode_set()
50 struct radeon_device *rdev = dev->dev_private; in radeon_legacy_rmx_mode_set()
52 int xres = mode->hdisplay; in radeon_legacy_rmx_mode_set()
53 int yres = mode->vdisplay; in radeon_legacy_rmx_mode_set()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
Dradeon_legacy_crtc.c2 * Copyright 2007-8 Advanced Micro Devices, Inc.
40 struct drm_device *dev = crtc->dev; in radeon_overscan_setup()
41 struct radeon_device *rdev = dev->dev_private; in radeon_overscan_setup()
44 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
45 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
46 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
52 struct drm_device *dev = crtc->dev; in radeon_legacy_rmx_mode_set()
53 struct radeon_device *rdev = dev->dev_private; in radeon_legacy_rmx_mode_set()
55 int xres = mode->hdisplay; in radeon_legacy_rmx_mode_set()
56 int yres = mode->vdisplay; in radeon_legacy_rmx_mode_set()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/
Ddce_clk_mgr.c2 * Copyright 2012-16 Advanced Micro Devices, Inc.
47 (clk_mgr->regs->reg)
51 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
68 /* ClocksStateInvalid - should not be used */
70 /* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
88 * (did - DENTIST_BASE_DID_1); in dentist_get_divider_from_did()
91 * (did - DENTIST_BASE_DID_2); in dentist_get_divider_from_did()
94 * (did - DENTIST_BASE_DID_3); in dentist_get_divider_from_did()
97 * (did - DENTIST_BASE_DID_4); in dentist_get_divider_from_did()
104 -if SS enabled on DP Ref clock and HW de-spreading enabled with SW
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/i915/
Dintel_display.c2 * Copyright © 2006-2007 Intel Corporation
184 mutex_lock(&dev_priv->sb_lock); in vlv_get_hpll_vco()
187 mutex_unlock(&dev_priv->sb_lock); in vlv_get_hpll_vco()
198 mutex_lock(&dev_priv->sb_lock); in vlv_get_cck_clock()
200 mutex_unlock(&dev_priv->sb_lock); in vlv_get_cck_clock()
214 if (dev_priv->hpll_freq == 0) in vlv_get_cck_clock_hpll()
215 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); in vlv_get_cck_clock_hpll()
218 dev_priv->hpll_freq); in vlv_get_cck_clock_hpll()
226 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", in intel_update_czclk()
229 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); in intel_update_czclk()
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/kernel/linux/linux-4.19/drivers/gpu/drm/rcar-du/
Drcar_lvds.c1 // SPDX-License-Identifier: GPL-2.0
3 * rcar_lvds.c -- R-Car LVDS Encoder
5 * Copyright (C) 2013-2018 Renesas Electronics Corporation
27 /* Keep in sync with the LVDCR0.LVMD hardware register values. */
56 bool enabled; member
70 iowrite32(data, lvds->mmio + reg); in rcar_lvds_write()
73 /* -----------------------------------------------------------------------------
81 return drm_panel_get_modes(lvds->panel); in rcar_lvds_connector_get_modes()
91 if (!state->crtc) in rcar_lvds_connector_atomic_check()
94 if (list_empty(&connector->modes)) { in rcar_lvds_connector_atomic_check()
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/kernel/linux/linux-5.10/drivers/phy/broadcom/
Dphy-brcm-usb-init.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * phy-brcm-usb-init.c - Broadcom USB Phy chip specific init functions
5 * Copyright (C) 2014-2017 Broadcom
16 #include "phy-brcm-usb-init.h"
133 (params->usb_reg_bits_map[USB_CTRL_##reg##_##field##_SELECTOR])
403 mask = params->usb_reg_bits_map[field]; in usb_ctrl_unset_family()
404 brcm_usb_ctrl_unset(params->regs[BRCM_REGS_CTRL] + reg_offset, mask); in usb_ctrl_unset_family()
413 mask = params->usb_reg_bits_map[field]; in usb_ctrl_set_family()
414 brcm_usb_ctrl_set(params->regs[BRCM_REGS_CTRL] + reg_offset, mask); in usb_ctrl_set_family()
460 /* reset USB 2.0 PLL */ in brcmusb_usb_phy_ldo_fix()
[all …]
/kernel/linux/linux-4.19/drivers/phy/broadcom/
Dphy-brcm-usb-init.c2 * phy-brcm-usb-init.c - Broadcom USB Phy chip specific init functions
4 * Copyright (C) 2014-2017 Broadcom
24 #include "phy-brcm-usb-init.h"
142 (params->usb_reg_bits_map[USB_CTRL_##reg##_##field##_SELECTOR])
429 mask = params->usb_reg_bits_map[field]; in usb_ctrl_unset_family()
430 reg = params->ctrl_regs + reg_offset; in usb_ctrl_unset_family()
441 mask = params->usb_reg_bits_map[field]; in usb_ctrl_set_family()
442 reg = params->ctrl_regs + reg_offset; in usb_ctrl_set_family()
505 /* reset USB 2.0 PLL */ in brcmusb_usb_phy_ldo_fix()
507 /* PLL reset period */ in brcmusb_usb_phy_ldo_fix()
[all …]
/kernel/linux/linux-4.19/drivers/net/wireless/broadcom/b43/
Db43.h1 /* SPDX-License-Identifier: GPL-2.0 */
61 /* 32-bit DMA */
68 /* 64-bit DMA */
203 #define B43_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
209 #define B43_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
211 #define B43_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
212 #define B43_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
234 #define B43_SHM_AUTOINC_R 0x0200 /* Auto-increment address on read */
235 #define B43_SHM_AUTOINC_W 0x0100 /* Auto-increment address on write */
330 #define B43_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/broadcom/b43/
Db43.h1 /* SPDX-License-Identifier: GPL-2.0 */
61 /* 32-bit DMA */
68 /* 64-bit DMA */
203 #define B43_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
209 #define B43_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
211 #define B43_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
212 #define B43_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
234 #define B43_SHM_AUTOINC_R 0x0200 /* Auto-increment address on read */
235 #define B43_SHM_AUTOINC_W 0x0100 /* Auto-increment address on write */
330 #define B43_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */
[all …]
/kernel/linux/linux-5.10/drivers/i2c/busses/
Di2c-mlxbf.c1 // SPDX-License-Identifier: GPL-2.0
53 * Note that the following SMBus, CAUSE, GPIO and PLL register addresses
55 * memory-mapped region whose addresses are specified in either the DT or
65 /* Reference clock for Bluefield - 156 MHz. */
68 /* Constant used to determine the PLL frequency. */
71 /* PLL registers. */
85 * as interrupt enabled bits.
122 * as interrupt enabled bits.
150 * SMBUS GW0 -> bits[26:25]
151 * SMBUS GW1 -> bits[28:27]
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/rcar-du/
Drcar_lvds.c1 // SPDX-License-Identifier: GPL-2.0
3 * rcar_lvds.c -- R-Car LVDS Encoder
5 * Copyright (C) 2013-2018 Renesas Electronics Corporation
34 /* Keep in sync with the LVDCR0.LVMD hardware register values. */
50 #define RCAR_LVDS_QUIRK_EXT_PLL BIT(3) /* Has extended PLL */
51 #define RCAR_LVDS_QUIRK_DUAL_LINK BIT(4) /* Supports dual-link operation */
88 iowrite32(data, lvds->mmio + reg); in rcar_lvds_write()
91 /* -----------------------------------------------------------------------------
99 return drm_panel_get_modes(lvds->panel, connector); in rcar_lvds_connector_get_modes()
111 if (!conn_state->crtc) in rcar_lvds_connector_atomic_check()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
Dintel_display.c2 * Copyright © 2006-2007 Intel Corporation
29 #include <linux/intel-iommu.h>
32 #include <linux/dma-resv.h>
208 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != in vlv_get_cck_clock()
222 if (dev_priv->hpll_freq == 0) in vlv_get_cck_clock_hpll()
223 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); in vlv_get_cck_clock_hpll()
225 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); in vlv_get_cck_clock_hpll()
237 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", in intel_update_czclk()
240 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", in intel_update_czclk()
241 dev_priv->czclk_freq); in intel_update_czclk()
[all …]
/kernel/linux/linux-5.10/include/linux/bcma/
Dbcma_driver_chipcommon.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 #define BCMA_CC_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
33 #define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
48 #define BCMA_CC_CAP_64BIT 0x08000000 /* 64-bit Backplane */
102 #define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */
104 #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
153 #define BCMA_CC_FLASHCTL_ST_DP 0x00b9 /* Deep Power-down */
155 #define BCMA_CC_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
156 #define BCMA_CC_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
234 #define BCMA_CC_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled…
[all …]
/kernel/linux/linux-4.19/include/linux/bcma/
Dbcma_driver_chipcommon.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 #define BCMA_CC_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
33 #define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
48 #define BCMA_CC_CAP_64BIT 0x08000000 /* 64-bit Backplane */
102 #define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */
104 #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
153 #define BCMA_CC_FLASHCTL_ST_DP 0x00b9 /* Deep Power-down */
155 #define BCMA_CC_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
156 #define BCMA_CC_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
234 #define BCMA_CC_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled…
[all …]
/kernel/linux/linux-4.19/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
Dmain.h48 * Usage example, e.g. a three-bit field (bits 4-6):
52 * regval = R_REG(osh, &regs->regfoo);
55 * W_REG(osh, &regs->regfoo, regval);
58 (((unsigned)1 << (width)) - 1)
67 /* max # supported core revisions (0 .. MAXCOREREV - 1) */
70 /* Double check that unsupported cores are not enabled */
76 #define BRCMS_SHORTSLOT_AUTO -1 /* Driver will manage Shortslot setting */
91 #define TXFID_QUEUE_MASK 0x0007 /* Bits 0-2 */
92 #define TXFID_SEQ_MASK 0x7FE0 /* Bits 5-15 */
132 /* PLL requests */
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
Dmain.h48 * Usage example, e.g. a three-bit field (bits 4-6):
52 * regval = R_REG(osh, &regs->regfoo);
55 * W_REG(osh, &regs->regfoo, regval);
58 (((unsigned)1 << (width)) - 1)
67 /* max # supported core revisions (0 .. MAXCOREREV - 1) */
70 /* Double check that unsupported cores are not enabled */
76 #define BRCMS_SHORTSLOT_AUTO -1 /* Driver will manage Shortslot setting */
91 #define TXFID_QUEUE_MASK 0x0007 /* Bits 0-2 */
92 #define TXFID_SEQ_MASK 0x7FE0 /* Bits 5-15 */
132 /* PLL requests */
[all …]
/kernel/linux/linux-5.10/arch/powerpc/platforms/512x/
Dclock-commonclk.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/mpc512x-clock.h>
25 /* helpers to keep the MCLK intermediates "somewhere" in our table */
88 * NFC IP block, output clocks, system PLL status query, different CPMF
89 * interpretation, no CFM, different fourth PSC/CAN mux0 input -- yet
292 val &= (1 << len) - 1; in get_bit_field()
296 /* get the SPMF and translate it into the "sys pll" multiplier */
305 spmf = get_bit_field(&clkregs->spmr, 24, 4); in get_spmf_mult()
326 divcode = get_bit_field(&clkregs->scfr2, 26, 6); in get_sys_div_x2()
[all …]
/kernel/linux/linux-4.19/arch/powerpc/platforms/512x/
Dclock-commonclk.c16 #include <linux/clk-provider.h>
25 #include <dt-bindings/clock/mpc512x-clock.h>
29 /* helpers to keep the MCLK intermediates "somewhere" in our table */
92 * NFC IP block, output clocks, system PLL status query, different CPMF
93 * interpretation, no CFM, different fourth PSC/CAN mux0 input -- yet
293 val &= (1 << len) - 1; in get_bit_field()
297 /* get the SPMF and translate it into the "sys pll" multiplier */
306 spmf = get_bit_field(&clkregs->spmr, 24, 4); in get_spmf_mult()
327 divcode = get_bit_field(&clkregs->scfr2, 26, 6); in get_sys_div_x2()
351 cpmf = get_bit_field(&clkregs->spmr, 16, 4); in get_cpmf_mult_x2()
[all …]
/kernel/linux/linux-5.10/include/linux/ssb/
Dssb_driver_chipcommon.h1 /* SPDX-License-Identifier: GPL-2.0-only */
30 #define SSB_CHIPCO_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
37 #define SSB_CHIPCO_CAP_PLLT 0x00038000 /* PLL Type */
52 #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
161 …e SSB_CHIPCO_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
163 …CLKCTL_IPLL 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable reque…
260 /** PMU PLL registers */
262 /* PMU rev 0 PLL registers */
276 /* PMU rev 1 PLL registers */
308 /* BCM4312 PLL resource numbers. */
[all …]
/kernel/linux/linux-4.19/include/linux/ssb/
Dssb_driver_chipcommon.h31 #define SSB_CHIPCO_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
38 #define SSB_CHIPCO_CAP_PLLT 0x00038000 /* PLL Type */
53 #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
162 …e SSB_CHIPCO_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
164 …CLKCTL_IPLL 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable reque…
261 /** PMU PLL registers */
263 /* PMU rev 0 PLL registers */
277 /* PMU rev 1 PLL registers */
309 /* BCM4312 PLL resource numbers. */
326 /* BCM4325 PLL resource numbers. */
[all …]

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