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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/ivsrcid/dcn/
Dirqsrcs_dcn_1_0.h30 …C_I2C_SW_DONE 1 // DC_I2C SW done DC_I2C_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level
33 … // DC_I2C DDC1 HW done DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
36 … // DC_I2C DDC2 HW done DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
39 … // DC_I2C DDC3 HW done DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
42 … // DC_I2C_DDC4 HW done DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
45 … // DC_I2C_DDC5 HW done DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
48 … // DC_I2C_DDC6 HW done DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
51 …DC_I2C_DDCVGA HW done DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
54 …DC1 read request DC_I2C_DDC1_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse
57 …DC2 read request DC_I2C_DDC2_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/amd/include/ivsrcid/
Dirqsrcs_dcn_1_0.h30 …C_I2C_SW_DONE 1 // DC_I2C SW done DC_I2C_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level
33 … // DC_I2C DDC1 HW done DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
36 … // DC_I2C DDC2 HW done DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
39 … // DC_I2C DDC3 HW done DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
42 … // DC_I2C_DDC4 HW done DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
45 … // DC_I2C_DDC5 HW done DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
48 … // DC_I2C_DDC6 HW done DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
51 …DC_I2C_DDCVGA HW done DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
54 …DC1 read request DC_I2C_DDC1_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse
57 …DC2 read request DC_I2C_DDC2_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse
[all …]
/kernel/linux/linux-4.19/fs/nilfs2/
Dbtree.c26 int level = NILFS_BTREE_LEVEL_DATA; in nilfs_btree_alloc_path() local
32 for (; level < NILFS_BTREE_LEVEL_MAX; level++) { in nilfs_btree_alloc_path()
33 path[level].bp_bh = NULL; in nilfs_btree_alloc_path()
34 path[level].bp_sib_bh = NULL; in nilfs_btree_alloc_path()
35 path[level].bp_index = 0; in nilfs_btree_alloc_path()
36 path[level].bp_oldreq.bpr_ptr = NILFS_BMAP_INVALID_PTR; in nilfs_btree_alloc_path()
37 path[level].bp_newreq.bpr_ptr = NILFS_BMAP_INVALID_PTR; in nilfs_btree_alloc_path()
38 path[level].bp_op = NULL; in nilfs_btree_alloc_path()
47 int level = NILFS_BTREE_LEVEL_DATA; in nilfs_btree_free_path() local
49 for (; level < NILFS_BTREE_LEVEL_MAX; level++) in nilfs_btree_free_path()
[all …]
/kernel/linux/linux-5.10/fs/nilfs2/
Dbtree.c26 int level = NILFS_BTREE_LEVEL_DATA; in nilfs_btree_alloc_path() local
32 for (; level < NILFS_BTREE_LEVEL_MAX; level++) { in nilfs_btree_alloc_path()
33 path[level].bp_bh = NULL; in nilfs_btree_alloc_path()
34 path[level].bp_sib_bh = NULL; in nilfs_btree_alloc_path()
35 path[level].bp_index = 0; in nilfs_btree_alloc_path()
36 path[level].bp_oldreq.bpr_ptr = NILFS_BMAP_INVALID_PTR; in nilfs_btree_alloc_path()
37 path[level].bp_newreq.bpr_ptr = NILFS_BMAP_INVALID_PTR; in nilfs_btree_alloc_path()
38 path[level].bp_op = NULL; in nilfs_btree_alloc_path()
47 int level = NILFS_BTREE_LEVEL_DATA; in nilfs_btree_free_path() local
49 for (; level < NILFS_BTREE_LEVEL_MAX; level++) in nilfs_btree_free_path()
[all …]
/kernel/linux/linux-5.10/arch/s390/include/asm/
Ddebug.h18 #define DEBUG_OFF_LEVEL -1 /* level where debug is switched off */
22 #define DEBUG_DEFAULT_LEVEL 3 /* initial debug level */
34 unsigned long level : 3; member
48 int level; member
99 debug_entry_t *debug_event_common(debug_info_t *id, int level,
102 debug_entry_t *debug_exception_common(debug_info_t *id, int level,
124 * level would be logged. Otherwise returns false.
127 * @level: debug level
130 * - %true if level is less or equal to the current debug level.
132 static inline bool debug_level_enabled(debug_info_t *id, int level) in debug_level_enabled() argument
[all …]
/kernel/linux/linux-5.10/arch/arm/
DKconfig.debug104 bool "Kernel low-level debugging functions (read help!)"
117 prompt "Kernel low-level debugging port"
121 bool "Kernel low-level debugging messages via Alpine UART0"
125 Say Y here if you want kernel low-level debugging support
129 bool "Kernel low-level debugging via asm9260 UART"
150 bool "Kernel low-level debugging on AT91RM9200, AT91SAM9, SAM9X60 DBGU"
154 Say Y here if you want kernel low-level debugging support
160 bool "Kernel low-level debugging on AT91SAM{9263,9G45,A5D3} DBGU"
164 Say Y here if you want kernel low-level debugging support
170 bool "Kernel low-level debugging on SAMA5D2 UART1"
[all …]
/kernel/linux/linux-5.10/arch/arm64/kernel/
Dcacheinfo.c13 #define MAX_CACHE_LEVEL 7 /* Max 7 level supported */
15 #define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1)) argument
16 #define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level)) argument
17 #define CLIDR_CTYPE(clidr, level) \ argument
18 (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))
29 static inline enum cache_type get_cache_type(int level) in get_cache_type() argument
33 if (level > MAX_CACHE_LEVEL) in get_cache_type()
36 return CLIDR_CTYPE(clidr, level); in get_cache_type()
40 enum cache_type type, unsigned int level) in ci_leaf_init() argument
42 this_leaf->level = level; in ci_leaf_init()
[all …]
/kernel/linux/linux-5.10/fs/xfs/scrub/
Dbtree.c28 int level, in __xchk_btree_process_error() argument
49 trace_xchk_ifork_btree_op_error(sc, cur, level, in __xchk_btree_process_error()
52 trace_xchk_btree_op_error(sc, cur, level, in __xchk_btree_process_error()
63 int level, in xchk_btree_process_error() argument
66 return __xchk_btree_process_error(sc, cur, level, error, in xchk_btree_process_error()
74 int level, in xchk_btree_xref_process_error() argument
77 return __xchk_btree_process_error(sc, cur, level, error, in xchk_btree_xref_process_error()
86 int level, in __xchk_btree_set_corrupt() argument
93 trace_xchk_ifork_btree_error(sc, cur, level, in __xchk_btree_set_corrupt()
96 trace_xchk_btree_error(sc, cur, level, in __xchk_btree_set_corrupt()
[all …]
Ddabtree.c32 int level, in xchk_da_process_error() argument
54 ds->state->path.blk[level].blkno), in xchk_da_process_error()
68 int level) in xchk_da_set_corrupt() argument
76 ds->state->path.blk[level].blkno), in xchk_da_set_corrupt()
83 int level) in xchk_da_btree_node_entry() argument
85 struct xfs_da_state_blk *blk = &ds->state->path.blk[level]; in xchk_da_btree_node_entry()
98 int level, in xchk_da_btree_hash() argument
107 if (hash < ds->hashes[level]) in xchk_da_btree_hash()
108 xchk_da_set_corrupt(ds, level); in xchk_da_btree_hash()
109 ds->hashes[level] = hash; in xchk_da_btree_hash()
[all …]
/kernel/linux/linux-5.10/security/selinux/ss/
Dcontext.h45 dst->range.level[0].sens = src->range.level[0].sens; in mls_context_cpy()
46 rc = ebitmap_cpy(&dst->range.level[0].cat, &src->range.level[0].cat); in mls_context_cpy()
50 dst->range.level[1].sens = src->range.level[1].sens; in mls_context_cpy()
51 rc = ebitmap_cpy(&dst->range.level[1].cat, &src->range.level[1].cat); in mls_context_cpy()
53 ebitmap_destroy(&dst->range.level[0].cat); in mls_context_cpy()
59 * Sets both levels in the MLS range of 'dst' to the low level of 'src'.
65 dst->range.level[0].sens = src->range.level[0].sens; in mls_context_cpy_low()
66 rc = ebitmap_cpy(&dst->range.level[0].cat, &src->range.level[0].cat); in mls_context_cpy_low()
70 dst->range.level[1].sens = src->range.level[0].sens; in mls_context_cpy_low()
71 rc = ebitmap_cpy(&dst->range.level[1].cat, &src->range.level[0].cat); in mls_context_cpy_low()
[all …]
/kernel/linux/linux-4.19/fs/xfs/scrub/
Dbtree.c35 int level, in __xchk_btree_process_error() argument
56 trace_xchk_ifork_btree_op_error(sc, cur, level, in __xchk_btree_process_error()
59 trace_xchk_btree_op_error(sc, cur, level, in __xchk_btree_process_error()
70 int level, in xchk_btree_process_error() argument
73 return __xchk_btree_process_error(sc, cur, level, error, in xchk_btree_process_error()
81 int level, in xchk_btree_xref_process_error() argument
84 return __xchk_btree_process_error(sc, cur, level, error, in xchk_btree_xref_process_error()
93 int level, in __xchk_btree_set_corrupt() argument
100 trace_xchk_ifork_btree_error(sc, cur, level, in __xchk_btree_set_corrupt()
103 trace_xchk_btree_error(sc, cur, level, in __xchk_btree_set_corrupt()
[all …]
Ddabtree.c40 int level, in xchk_da_process_error() argument
62 ds->state->path.blk[level].blkno), in xchk_da_process_error()
76 int level) in xchk_da_set_corrupt() argument
84 ds->state->path.blk[level].blkno), in xchk_da_set_corrupt()
88 /* Find an entry at a certain level in a da btree. */
92 int level, in xchk_da_btree_entry() argument
100 blk = &ds->state->path.blk[level]; in xchk_da_btree_entry()
128 int level, in xchk_da_btree_hash() argument
138 if (hash < ds->hashes[level]) in xchk_da_btree_hash()
139 xchk_da_set_corrupt(ds, level); in xchk_da_btree_hash()
[all …]
/kernel/linux/linux-4.19/arch/arm/
DKconfig.debug97 bool "Kernel low-level debugging functions (read help!)"
110 prompt "Kernel low-level debugging port"
114 bool "Kernel low-level debugging messages via Alpine UART0"
118 Say Y here if you want kernel low-level debugging support
122 bool "Kernel low-level debugging via asm9260 UART"
143 bool "Kernel low-level debugging on AT91RM9200, AT91SAM9 DBGU"
147 Say Y here if you want kernel low-level debugging support
153 bool "Kernel low-level debugging on AT91SAM{9263,9G45,A5D3} DBGU"
157 Say Y here if you want kernel low-level debugging support
163 bool "Kernel low-level debugging on SAMA5D2 UART1"
[all …]
/kernel/linux/linux-4.19/arch/arm64/kernel/
Dcacheinfo.c24 #define MAX_CACHE_LEVEL 7 /* Max 7 level supported */
26 #define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1)) argument
27 #define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level)) argument
28 #define CLIDR_CTYPE(clidr, level) \ argument
29 (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))
31 static inline enum cache_type get_cache_type(int level) in get_cache_type() argument
35 if (level > MAX_CACHE_LEVEL) in get_cache_type()
38 return CLIDR_CTYPE(clidr, level); in get_cache_type()
42 enum cache_type type, unsigned int level) in ci_leaf_init() argument
44 this_leaf->level = level; in ci_leaf_init()
[all …]
/kernel/linux/linux-5.10/arch/sparc/include/uapi/asm/
Dtraps.h46 #define SP_TRAP_IRQ1 0x11 /* IRQ level 1 */
47 #define SP_TRAP_IRQ2 0x12 /* IRQ level 2 */
48 #define SP_TRAP_IRQ3 0x13 /* IRQ level 3 */
49 #define SP_TRAP_IRQ4 0x14 /* IRQ level 4 */
50 #define SP_TRAP_IRQ5 0x15 /* IRQ level 5 */
51 #define SP_TRAP_IRQ6 0x16 /* IRQ level 6 */
52 #define SP_TRAP_IRQ7 0x17 /* IRQ level 7 */
53 #define SP_TRAP_IRQ8 0x18 /* IRQ level 8 */
54 #define SP_TRAP_IRQ9 0x19 /* IRQ level 9 */
55 #define SP_TRAP_IRQ10 0x1a /* IRQ level 10 */
[all …]
/kernel/linux/linux-4.19/arch/sparc/include/uapi/asm/
Dtraps.h46 #define SP_TRAP_IRQ1 0x11 /* IRQ level 1 */
47 #define SP_TRAP_IRQ2 0x12 /* IRQ level 2 */
48 #define SP_TRAP_IRQ3 0x13 /* IRQ level 3 */
49 #define SP_TRAP_IRQ4 0x14 /* IRQ level 4 */
50 #define SP_TRAP_IRQ5 0x15 /* IRQ level 5 */
51 #define SP_TRAP_IRQ6 0x16 /* IRQ level 6 */
52 #define SP_TRAP_IRQ7 0x17 /* IRQ level 7 */
53 #define SP_TRAP_IRQ8 0x18 /* IRQ level 8 */
54 #define SP_TRAP_IRQ9 0x19 /* IRQ level 9 */
55 #define SP_TRAP_IRQ10 0x1a /* IRQ level 10 */
[all …]
/kernel/linux/linux-4.19/arch/sparc/kernel/
Dcpumap.c26 /* Increment rover every time level is visited */
34 int level; member
43 int start_index; /* Index of first node of a level in a cpuinfo tree */
44 int end_index; /* Index of last node of a level in a cpuinfo tree */
45 int num_nodes; /* Number of nodes in a level in a cpuinfo tree */
51 /* Offsets into nodes[] for each level of the tree */
52 struct cpuinfo_level level[CPUINFO_LVL_MAX]; member
96 static int cpuinfo_id(int cpu, int level) in cpuinfo_id() argument
100 switch (level) { in cpuinfo_id()
121 * end index, and number of nodes for each level in the cpuinfo tree. The
[all …]
/kernel/linux/linux-5.10/arch/sparc/kernel/
Dcpumap.c26 /* Increment rover every time level is visited */
34 int level; member
43 int start_index; /* Index of first node of a level in a cpuinfo tree */
44 int end_index; /* Index of last node of a level in a cpuinfo tree */
45 int num_nodes; /* Number of nodes in a level in a cpuinfo tree */
51 /* Offsets into nodes[] for each level of the tree */
52 struct cpuinfo_level level[CPUINFO_LVL_MAX]; member
96 static int cpuinfo_id(int cpu, int level) in cpuinfo_id() argument
100 switch (level) { in cpuinfo_id()
121 * end index, and number of nodes for each level in the cpuinfo tree. The
[all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_z13/
Dextended.json7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
14 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
28 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
35 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
42 …ption": "A directory write to the Level-1 Data cache directory where the returned cache line was s…
49 …"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation …
56 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
63 …n": "A directory write to the Level-1 Instruction cache directory where the returned cache line wa…
70 …"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arr…
[all …]
/kernel/linux/linux-4.19/tools/perf/pmu-events/arch/s390/cf_z13/
Dextended.json7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
14 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
28 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
35 …r:132 Name:DTLB1_GPAGE_WRITES A translation entry has been written to the Level-1 Data Translation…
42 …ption": "A directory write to the Level-1 Data cache directory where the returned cache line was s…
49 …"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation …
56 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
63 …n": "A directory write to the Level-1 Instruction cache directory where the returned cache line wa…
70 …"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arr…
[all …]
/kernel/linux/linux-4.19/security/selinux/ss/
Dcontext.h45 dst->range.level[0].sens = src->range.level[0].sens; in mls_context_cpy()
46 rc = ebitmap_cpy(&dst->range.level[0].cat, &src->range.level[0].cat); in mls_context_cpy()
50 dst->range.level[1].sens = src->range.level[1].sens; in mls_context_cpy()
51 rc = ebitmap_cpy(&dst->range.level[1].cat, &src->range.level[1].cat); in mls_context_cpy()
53 ebitmap_destroy(&dst->range.level[0].cat); in mls_context_cpy()
59 * Sets both levels in the MLS range of 'dst' to the low level of 'src'.
65 dst->range.level[0].sens = src->range.level[0].sens; in mls_context_cpy_low()
66 rc = ebitmap_cpy(&dst->range.level[0].cat, &src->range.level[0].cat); in mls_context_cpy_low()
70 dst->range.level[1].sens = src->range.level[0].sens; in mls_context_cpy_low()
71 rc = ebitmap_cpy(&dst->range.level[1].cat, &src->range.level[0].cat); in mls_context_cpy_low()
[all …]
/kernel/linux/linux-4.19/tools/perf/pmu-events/arch/s390/cf_zec12/
Dextended.json7 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
14 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
21 …ption": "A directory write to the Level-1 Data cache directory where the returned cache line was s…
28 …n": "A directory write to the Level-1 Instruction cache directory where the returned cache line wa…
35 …ption": "A directory write to the Level-1 Data cache directory where the returned cache line was s…
42 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
49 …"PublicDescription": "A directory write to the Level-1 Data cache where the installed cache line w…
56 …"PublicDescription": "A directory write to the Level-1 Instruction cache where the installed cache…
63 …"PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a …
70 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
[all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_zec12/
Dextended.json7 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
14 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
21 …ption": "A directory write to the Level-1 Data cache directory where the returned cache line was s…
28 …n": "A directory write to the Level-1 Instruction cache directory where the returned cache line wa…
35 …ption": "A directory write to the Level-1 Data cache directory where the returned cache line was s…
42 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
49 …"PublicDescription": "A directory write to the Level-1 Data cache where the installed cache line w…
56 …"PublicDescription": "A directory write to the Level-1 Instruction cache where the installed cache…
63 …"PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a …
70 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
[all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_z14/
Dextended.json7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
21 …he data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on th…
28 …was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-me…
35 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB"
42 …ption": "A directory write to the Level-1 Data cache directory where the returned cache line was s…
56 …ruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cach…
63 …n": "A directory write to the Level-1 Instruction cache directory where the returned cache line wa…
70 …cDescription": "A translation entry was written into the Page Table Entry array in the Level-2 TLB"
77 …he Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB"
84 "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle"
[all …]
/kernel/linux/linux-4.19/tools/perf/pmu-events/arch/s390/cf_z14/
Dextended.json7 …"PublicDescription": "Counter:128 Name:L1D_RO_EXCL_WRITES A directory write to the Level-1 Data ca…
21 …he data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on th…
28 …was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-me…
35 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB"
42 …ption": "A directory write to the Level-1 Data cache directory where the returned cache line was s…
56 …ruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cach…
63 …n": "A directory write to the Level-1 Instruction cache directory where the returned cache line wa…
70 …cDescription": "A translation entry was written into the Page Table Entry array in the Level-2 TLB"
77 …he Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB"
84 "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle"
[all …]

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