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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mfd/
Dst,stpmic1.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - pascal Paillet <p.paillet@st.com>
24 "#interrupt-cells":
27 interrupt-controller: true
36 const: st,stpmic1-onkey
40 - description: onkey-falling, happens when onkey is pressed. IT_PONKEY_F of pmic
41 - description: onkey-rising, happens when onkey is released. IT_PONKEY_R of pmic
43 interrupt-names:
[all …]
/kernel/linux/linux-5.10/drivers/reset/
Dreset-ti-syscon.c2 * TI SYSCON regmap reset driver
4 * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
23 #include <linux/reset-controller.h>
25 #include <dt-bindings/reset/ti-syscon.h>
28 * struct ti_syscon_reset_control - reset control structure
29 * @assert_offset: reset assert control register offset from syscon base
30 * @assert_bit: reset assert bit in the reset assert control register
31 * @deassert_offset: reset deassert control register offset from syscon base
32 * @deassert_bit: reset deassert bit in the reset deassert control register
33 * @status_offset: reset status register offset from syscon base
[all …]
Dreset-pistachio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Pistachio SoC Reset Controller driver
14 #include <linux/reset-controller.h>
18 #include <dt-bindings/reset/pistachio-resets.h>
59 return -EINVAL; in pistachio_reset_shift()
67 u32 mask; in pistachio_reset_assert() local
74 mask = BIT(shift); in pistachio_reset_assert()
76 return regmap_update_bits(rd->periph_regs, PISTACHIO_SOFT_RESET, in pistachio_reset_assert()
77 mask, mask); in pistachio_reset_assert()
84 u32 mask; in pistachio_reset_deassert() local
[all …]
Dreset-a10sr.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Reset driver for Altera Arria10 MAX5 System Resource Chip
7 * Adapted from reset-socfpga.c
11 #include <linux/mfd/altera-a10sr.h>
15 #include <linux/reset-controller.h>
17 #include <dt-bindings/reset/altr,rst-mgr-a10sr.h>
40 return -EINVAL; in a10sr_reset_shift()
49 u8 mask = ALTR_A10SR_REG_BIT_MASK(offset); in a10sr_reset_update() local
52 return regmap_update_bits(a10r->regmap, index, mask, assert ? 0 : mask); in a10sr_reset_update()
73 u8 mask = ALTR_A10SR_REG_BIT_MASK(offset); in a10sr_reset_status() local
[all …]
/kernel/linux/linux-4.19/drivers/reset/
Dreset-ti-syscon.c2 * TI SYSCON regmap reset driver
4 * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
23 #include <linux/reset-controller.h>
25 #include <dt-bindings/reset/ti-syscon.h>
28 * struct ti_syscon_reset_control - reset control structure
29 * @assert_offset: reset assert control register offset from syscon base
30 * @assert_bit: reset assert bit in the reset assert control register
31 * @deassert_offset: reset deassert control register offset from syscon base
32 * @deassert_bit: reset deassert bit in the reset deassert control register
33 * @status_offset: reset status register offset from syscon base
[all …]
Dreset-pistachio.c2 * Pistachio SoC Reset Controller driver
17 #include <linux/reset-controller.h>
21 #include <dt-bindings/reset/pistachio-resets.h>
62 return -EINVAL; in pistachio_reset_shift()
70 u32 mask; in pistachio_reset_assert() local
77 mask = BIT(shift); in pistachio_reset_assert()
79 return regmap_update_bits(rd->periph_regs, PISTACHIO_SOFT_RESET, in pistachio_reset_assert()
80 mask, mask); in pistachio_reset_assert()
87 u32 mask; in pistachio_reset_deassert() local
94 mask = BIT(shift); in pistachio_reset_deassert()
[all …]
Dreset-a10sr.c16 * Reset driver for Altera Arria10 MAX5 System Resource Chip
18 * Adapted from reset-socfpga.c
22 #include <linux/mfd/altera-a10sr.h>
26 #include <linux/reset-controller.h>
28 #include <dt-bindings/reset/altr,rst-mgr-a10sr.h>
51 return -EINVAL; in a10sr_reset_shift()
60 u8 mask = ALTR_A10SR_REG_BIT_MASK(offset); in a10sr_reset_update() local
63 return regmap_update_bits(a10r->regmap, index, mask, assert ? 0 : mask); in a10sr_reset_update()
84 u8 mask = ALTR_A10SR_REG_BIT_MASK(offset); in a10sr_reset_status() local
88 ret = regmap_read(a10r->regmap, index, &value); in a10sr_reset_status()
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/kernel/linux/linux-5.10/arch/arm/mach-omap2/
Dprminst44xx.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include "prcm-common.h"
23 #include "prm-regbits-44xx.h"
34 * omap_prm_base_init - Populates the prm partitions
75 /* Read-modify-write a register in PRM. Caller must lock */
76 u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst, in omap4_prminst_rmw_inst_reg_bits() argument
82 v &= ~mask; in omap4_prminst_rmw_inst_reg_bits()
90 * omap4_prminst_is_hardreset_asserted - read the HW reset line state of
93 * @shift: register bit shift corresponding to the reset line to check
97 * -EINVAL upon parameter error.
[all …]
Dprm2xxx_3xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010-2011 Texas Instruments, Inc.
18 #include "prm-regbits-24xx.h"
22 * omap2_prm_is_hardreset_asserted - read the HW reset line state of
24 * @shift: register bit shift corresponding to the reset line to check
31 * -EINVAL if called while running on a non-OMAP2/3 chip.
40 * omap2_prm_assert_hardreset - assert the HW reset line of a submodule
41 * @shift: register bit shift corresponding to the reset line to assert
47 * reset line to be asserted / deasserted in order to fully enable the
48 * IP. These modules may have multiple hard-reset lines that reset
[all …]
Dprm33xx.c4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
24 #include "prm-regbits-33xx.h"
42 /* Read-modify-write a register in PRM. Caller must lock */
43 static u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx) in am33xx_prm_rmw_reg_bits() argument
48 v &= ~mask; in am33xx_prm_rmw_reg_bits()
56 * am33xx_prm_is_hardreset_asserted - read the HW reset line state of
58 * @shift: register bit shift corresponding to the reset line to check
65 * -EINVAL upon parameter error.
80 * am33xx_prm_assert_hardreset - assert the HW reset line of a submodule
81 * @shift: register bit shift corresponding to the reset line to assert
[all …]
/kernel/linux/linux-4.19/arch/arm/mach-omap2/
Dprminst44xx.c21 #include "prcm-common.h"
26 #include "prm-regbits-44xx.h"
37 * omap_prm_base_init - Populates the prm partitions
78 /* Read-modify-write a register in PRM. Caller must lock */
79 u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst, in omap4_prminst_rmw_inst_reg_bits() argument
85 v &= ~mask; in omap4_prminst_rmw_inst_reg_bits()
93 * omap4_prminst_is_hardreset_asserted - read the HW reset line state of
96 * @shift: register bit shift corresponding to the reset line to check
100 * -EINVAL upon parameter error.
115 * omap4_prminst_assert_hardreset - assert the HW reset line of a submodule
[all …]
Dprm2xxx_3xxx.c4 * Copyright (C) 2010-2011 Texas Instruments, Inc.
21 #include "prm-regbits-24xx.h"
25 * omap2_prm_is_hardreset_asserted - read the HW reset line state of
27 * @shift: register bit shift corresponding to the reset line to check
34 * -EINVAL if called while running on a non-OMAP2/3 chip.
43 * omap2_prm_assert_hardreset - assert the HW reset line of a submodule
44 * @shift: register bit shift corresponding to the reset line to assert
50 * reset line to be asserted / deasserted in order to fully enable the
51 * IP. These modules may have multiple hard-reset lines that reset
53 * place the submodule into reset. Returns 0 upon success or -EINVAL
[all …]
Dprm33xx.c4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
24 #include "prm-regbits-33xx.h"
42 /* Read-modify-write a register in PRM. Caller must lock */
43 static u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx) in am33xx_prm_rmw_reg_bits() argument
48 v &= ~mask; in am33xx_prm_rmw_reg_bits()
56 * am33xx_prm_is_hardreset_asserted - read the HW reset line state of
58 * @shift: register bit shift corresponding to the reset line to check
65 * -EINVAL upon parameter error.
80 * am33xx_prm_assert_hardreset - assert the HW reset line of a submodule
81 * @shift: register bit shift corresponding to the reset line to assert
[all …]
/kernel/linux/linux-5.10/drivers/media/pci/cx18/
Dcx18-gpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Derived from ivtv-gpio.c
11 #include "cx18-driver.h"
12 #include "cx18-io.h"
13 #include "cx18-cards.h"
14 #include "cx18-gpio.h"
15 #include "tuner-xc2028.h"
27 * HVR-1600 GPIO pins, courtesy of Hauppauge:
29 * gpio0: zilog ir process reset pin
31 * gpio12: cx24227 reset pin
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/power/reset/
Dsyscon-reboot.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/reset/syscon-reboot.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic SYSCON mapped register reset driver
10 - Sebastian Reichel <sre@kernel.org>
13 This is a generic reset driver using syscon to map the reset register.
14 The reset is generally performed with a write to the reset register
16 mask defined in the reboot node. Default will be little endian mode, 32 bit
18 parental dt-node. So the SYSCON reboot node should be represented as a
[all …]
/kernel/linux/linux-4.19/drivers/media/pci/cx18/
Dcx18-gpio.c4 * Derived from ivtv-gpio.c
20 #include "cx18-driver.h"
21 #include "cx18-io.h"
22 #include "cx18-cards.h"
23 #include "cx18-gpio.h"
24 #include "tuner-xc2028.h"
36 * HVR-1600 GPIO pins, courtesy of Hauppauge:
38 * gpio0: zilog ir process reset pin
40 * gpio12: cx24227 reset pin
41 * gpio13: cs5345 reset pin
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/power/reset/
Dsyscon-reboot.txt1 Generic SYSCON mapped register reset driver
3 This is a generic reset driver using syscon to map the reset register.
4 The reset is generally performed with a write to the reset register
6 with the mask defined in the reboot node.
9 - compatible: should contain "syscon-reboot"
10 - regmap: this is phandle to the register map node
11 - offset: offset in the register map for the reboot register (in bytes)
12 - mask: the reset value written to the reboot register (32 bit access)
19 compatible = "syscon-reboot";
22 mask = <0x1>;
/kernel/linux/linux-5.10/drivers/clk/qcom/
Dreset.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/reset-controller.h>
12 #include "reset.h"
16 rcdev->ops->assert(rcdev, id); in qcom_reset()
18 rcdev->ops->deassert(rcdev, id); in qcom_reset()
27 u32 mask; in qcom_reset_assert() local
30 map = &rst->reset_map[id]; in qcom_reset_assert()
31 mask = BIT(map->bit); in qcom_reset_assert()
33 return regmap_update_bits(rst->regmap, map->reg, mask, mask); in qcom_reset_assert()
41 u32 mask; in qcom_reset_deassert() local
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/kernel/linux/linux-5.10/include/linux/input/
Dadp5589.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright 2010-2011 Analog Devices Inc.
47 #define ADP5589_GPIMAPSIZE_MAX (ADP5589_GPI_PIN_END - ADP5589_GPI_PIN_BASE + 1)
76 #define ADP5585_GPIMAPSIZE_MAX (ADP5585_GPI_PIN_END - ADP5585_GPI_PIN_BASE + 1)
110 /* ADP5589 Mask Bits:
114 * ---------------- BIT ------------------
127 /* ADP5585 Mask Bits:
131 * ---- BIT -- -----------
149 unsigned keypad_en_mask; /* Keypad (Rows/Columns) enable mask */
158 unsigned char reset_cfg; /* Reset config */
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/kernel/linux/linux-4.19/include/linux/input/
Dadp5589.h4 * Copyright 2010-2011 Analog Devices Inc.
6 * Licensed under the GPL-2.
48 #define ADP5589_GPIMAPSIZE_MAX (ADP5589_GPI_PIN_END - ADP5589_GPI_PIN_BASE + 1)
77 #define ADP5585_GPIMAPSIZE_MAX (ADP5585_GPI_PIN_END - ADP5585_GPI_PIN_BASE + 1)
111 /* ADP5589 Mask Bits:
115 * ---------------- BIT ------------------
128 /* ADP5585 Mask Bits:
132 * ---- BIT -- -----------
150 unsigned keypad_en_mask; /* Keypad (Rows/Columns) enable mask */
159 unsigned char reset_cfg; /* Reset config */
[all …]
/kernel/linux/linux-5.10/drivers/input/misc/
Dpmic8xxx-pwrkey.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
33 /* Regulator control registers for shutdown/reset */
53 /* Buck TEST2 registers for shutdown/reset */
72 * struct pmic8xxx_pwrkey - pmic8xxx pwrkey information
108 enable_irq_wake(pwrkey->key_press_irq); in pmic8xxx_pwrkey_suspend()
118 disable_irq_wake(pwrkey->key_press_irq); in pmic8xxx_pwrkey_resume()
130 u8 mask, val; in pmic8xxx_pwrkey_shutdown() local
131 bool reset = system_state == SYSTEM_RESTART; in pmic8xxx_pwrkey_shutdown() local
133 if (pwrkey->shutdown_fn) { in pmic8xxx_pwrkey_shutdown()
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/kernel/linux/linux-4.19/drivers/input/misc/
Dpmic8xxx-pwrkey.c1 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
41 /* Regulator control registers for shutdown/reset */
61 /* Buck TEST2 registers for shutdown/reset */
80 * struct pmic8xxx_pwrkey - pmic8xxx pwrkey information
116 enable_irq_wake(pwrkey->key_press_irq); in pmic8xxx_pwrkey_suspend()
126 disable_irq_wake(pwrkey->key_press_irq); in pmic8xxx_pwrkey_resume()
138 u8 mask, val; in pmic8xxx_pwrkey_shutdown() local
139 bool reset = system_state == SYSTEM_RESTART; in pmic8xxx_pwrkey_shutdown() local
141 if (pwrkey->shutdown_fn) { in pmic8xxx_pwrkey_shutdown()
142 error = pwrkey->shutdown_fn(pwrkey, reset); in pmic8xxx_pwrkey_shutdown()
[all …]
/kernel/linux/linux-4.19/drivers/clk/qcom/
Dreset.c17 #include <linux/reset-controller.h>
20 #include "reset.h"
24 rcdev->ops->assert(rcdev, id); in qcom_reset()
26 rcdev->ops->deassert(rcdev, id); in qcom_reset()
35 u32 mask; in qcom_reset_assert() local
38 map = &rst->reset_map[id]; in qcom_reset_assert()
39 mask = BIT(map->bit); in qcom_reset_assert()
41 return regmap_update_bits(rst->regmap, map->reg, mask, mask); in qcom_reset_assert()
49 u32 mask; in qcom_reset_deassert() local
52 map = &rst->reset_map[id]; in qcom_reset_deassert()
[all …]
/kernel/linux/linux-4.19/arch/mips/include/asm/sn/sn0/
Dhubni.h8 * Copyright (C) 1992-1997, 1999 Silicon Graphics, Inc.
28 #define NI_PORT_RESET 0x600008 /* Reset the network interface */
70 * NI_STATUS_REV_ID mask and shift definitions
79 #define NSRI_DOWNREASON_MASK (UINT64_CAST 0x1 << 28) /* out of reset. */
102 /* NI_PORT_RESET mask definitions */
104 #define NPR_PORTRESET (UINT64_CAST 1 << 7) /* Send warm reset */
105 #define NPR_LINKRESET (UINT64_CAST 1 << 1) /* Send link reset */
106 #define NPR_LOCALRESET (UINT64_CAST 1) /* Reset entire hub */
108 /* NI_PROTECTION mask and shift definitions */
112 /* NI_GLOBAL_PARMS mask and shift definitions */
[all …]
/kernel/linux/linux-5.10/arch/mips/include/asm/sn/sn0/
Dhubni.h8 * Copyright (C) 1992-1997, 1999 Silicon Graphics, Inc.
28 #define NI_PORT_RESET 0x600008 /* Reset the network interface */
70 * NI_STATUS_REV_ID mask and shift definitions
79 #define NSRI_DOWNREASON_MASK (UINT64_CAST 0x1 << 28) /* out of reset. */
102 /* NI_PORT_RESET mask definitions */
104 #define NPR_PORTRESET (UINT64_CAST 1 << 7) /* Send warm reset */
105 #define NPR_LINKRESET (UINT64_CAST 1 << 1) /* Send link reset */
106 #define NPR_LOCALRESET (UINT64_CAST 1) /* Reset entire hub */
108 /* NI_PROTECTION mask and shift definitions */
112 /* NI_GLOBAL_PARMS mask and shift definitions */
[all …]

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