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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/iio/adc/
Damlogic,meson-saradc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/amlogic,meson-saradc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
18 - const: amlogic,meson-saradc
19 - items:
20 - enum:
21 - amlogic,meson8-saradc
22 - amlogic,meson8b-saradc
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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/iio/adc/
Damlogic,meson-saradc.txt4 - compatible: depending on the SoC this should be one of:
5 - "amlogic,meson8-saradc" for Meson8
6 - "amlogic,meson8b-saradc" for Meson8b
7 - "amlogic,meson8m2-saradc" for Meson8m2
8 - "amlogic,meson-gxbb-saradc" for GXBB
9 - "amlogic,meson-gxl-saradc" for GXL
10 - "amlogic,meson-gxm-saradc" for GXM
11 - "amlogic,meson-axg-saradc" for AXG
12 along with the generic "amlogic,meson-saradc"
13 - reg: the physical base address and length of the registers
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/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dmeson8b.dtsi5 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/clock/meson8b-clkc.h>
48 #include <dt-bindings/gpio/meson8b-gpio.h>
49 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
50 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
55 #address-cells = <1>;
56 #size-cells = <0>;
60 compatible = "arm,cortex-a5";
61 next-level-cache = <&L2>;
63 enable-method = "amlogic,meson8b-smp";
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Dmeson8.dtsi4 * This file is dual-licensed: you can use it either under the terms
46 #include <dt-bindings/clock/meson8b-clkc.h>
47 #include <dt-bindings/gpio/meson8-gpio.h>
48 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
49 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
57 #address-cells = <1>;
58 #size-cells = <0>;
62 compatible = "arm,cortex-a9";
63 next-level-cache = <&L2>;
65 enable-method = "amlogic,meson8-smp";
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dmeson8b.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 #include <dt-bindings/clock/meson8-ddr-clkc.h>
8 #include <dt-bindings/clock/meson8b-clkc.h>
9 #include <dt-bindings/gpio/meson8b-gpio.h>
10 #include <dt-bindings/power/meson8-power.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a5";
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Dmeson8b-mxq.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
11 #include "meson8b.dtsi"
15 compatible = "tronfy,mxq", "amlogic,meson8b";
22 stdout-path = "serial0:115200n8";
30 iio-hwmon {
31 compatible = "iio-hwmon";
32 io-channels = <&saradc 8>;
35 vcck: regulator-vcck {
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Dmeson8m2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
14 compatible = "amlogic,meson8m2-clkc", "amlogic,meson8-clkc";
19 /delete-node/ video-lut@20;
21 canvas: video-lut@48 {
22 compatible = "amlogic,meson8m2-canvas", "amlogic,canvas";
28 compatible = "amlogic,meson8m2-dwmac", "snps,dwmac";
35 clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
37 reset-names = "stmmaceth";
41 compatible = "amlogic,meson8m2-aobus-pinctrl",
42 "amlogic,meson8-aobus-pinctrl";
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Dmeson8.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 #include <dt-bindings/clock/meson8-ddr-clkc.h>
7 #include <dt-bindings/clock/meson8b-clkc.h>
8 #include <dt-bindings/gpio/meson8-gpio.h>
9 #include <dt-bindings/power/meson8-power.h>
10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
19 #address-cells = <1>;
20 #size-cells = <0>;
24 compatible = "arm,cortex-a9";
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Dmeson8b-odroidc1.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include "meson8b.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
12 model = "Hardkernel ODROID-C1";
13 compatible = "hardkernel,odroid-c1", "amlogic,meson8b";
22 stdout-path = "serial0:115200n8";
30 emmc_pwrseq: emmc-pwrseq {
31 compatible = "mmc-pwrseq-emmc";
32 reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
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Dmeson8b-ec100.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
11 #include "meson8b.dtsi"
15 compatible = "endless,ec100", "amlogic,meson8b";
22 stdout-path = "serial0:115200n8";
30 emmc_pwrseq: emmc-pwrseq {
31 compatible = "mmc-pwrseq-emmc";
32 reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
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/kernel/linux/linux-4.19/drivers/iio/adc/
Dmeson_saradc.c16 #include <linux/clk-provider.h>
100 (8 + (((_chan) - 2) * 3))
158 * and u-boot source served as reference). These only seem to be relevant on
270 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval); in meson_sar_adc_get_fifo_count()
281 tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias; in meson_sar_adc_calib_val()
283 return clamp(tmp, 0, (1 << priv->data->param->resolution) - 1); in meson_sar_adc_calib_val()
298 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval); in meson_sar_adc_wait_busy_clear()
299 } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--); in meson_sar_adc_wait_busy_clear()
302 return -ETIMEDOUT; in meson_sar_adc_wait_busy_clear()
314 if(!wait_for_completion_timeout(&priv->done, in meson_sar_adc_read_raw_sample()
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/kernel/linux/linux-5.10/drivers/iio/adc/
Dmeson_saradc.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
15 #include <linux/nvmem-consumer.h>
96 (8 + (((_chan) - 2) * 3))
153 * and u-boot source served as reference). These only seem to be relevant on
306 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval); in meson_sar_adc_get_fifo_count()
317 tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias; in meson_sar_adc_calib_val()
319 return clamp(tmp, 0, (1 << priv->param->resolution) - 1); in meson_sar_adc_calib_val()
334 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval); in meson_sar_adc_wait_busy_clear()
335 } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--); in meson_sar_adc_wait_busy_clear()
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