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/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/
Dpipeline.json10 … DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre…
20 …"BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being p…
25 "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed"
30 …"BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instruc…
40 … "BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation."
/kernel/linux/linux-4.19/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/
Dpipeline.json10 … DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre…
20 …"BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being p…
25 "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed"
30 …"BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instruc…
40 … "BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation."
/kernel/linux/linux-5.10/arch/powerpc/platforms/8xx/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
33 bool "Embedded Planet EP88xC (a.k.a. CWH-PPC-885XN-VE)"
39 MPC885 Evaluation System and/or the CWH-PPC-885XN-VE.
42 bool "Analogue & Micro Adder 875"
45 This enables support for the Analogue & Micro Adder 875
56 menu "Freescale Ethernet driver platform-specific options"
76 Enable FEC2 to serve as 2-nd Ethernet channel. Note that SMC2
77 (often 2-nd UART) will not work if this is enabled.
83 Enable SCC3 to serve as 2-nd Ethernet channel. Note that SMC1
84 (often 1-nd UART) will not work if this is enabled.
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/iommu/
Drenesas,ipmmu-vmsa.txt1 * Renesas VMSA-Compatible IOMMU
5 connected to the IPMMU through a port called micro-TLB.
10 - compatible: Must contain SoC-specific and generic entry below in case
11 the device is compatible with the R-Car Gen2 VMSA-compatible IPMMU.
13 - "renesas,ipmmu-r8a73a4" for the R8A73A4 (R-Mobile APE6) IPMMU.
14 - "renesas,ipmmu-r8a7743" for the R8A7743 (RZ/G1M) IPMMU.
15 - "renesas,ipmmu-r8a7745" for the R8A7745 (RZ/G1E) IPMMU.
16 - "renesas,ipmmu-r8a7790" for the R8A7790 (R-Car H2) IPMMU.
17 - "renesas,ipmmu-r8a7791" for the R8A7791 (R-Car M2-W) IPMMU.
18 - "renesas,ipmmu-r8a7793" for the R8A7793 (R-Car M2-N) IPMMU.
[all …]
Dmsm,iommu-v0.txt5 of the CPU, each connected to the IOMMU through a port called micro-TLB.
9 - compatible: Must contain "qcom,apq8064-iommu".
10 - reg: Base address and size of the IOMMU registers.
11 - interrupts: Specifiers for the MMU fault interrupts. For instances that
12 support secure mode two interrupts must be specified, for non-secure and
15 - #iommu-cells: The number of cells needed to specify the stream id. This
17 - qcom,ncb: The total number of context banks in the IOMMU.
18 - clocks : List of clocks to be used during SMMU register access. See
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
21 here, there must be a corresponding entry in clock-names
[all …]
/kernel/linux/linux-4.19/arch/arm/kernel/
Dperf_event_v6.c1 // SPDX-License-Identifier: GPL-2.0
17 * - change the counter to count the ETMEXTOUT[0] signal (0x20). This
19 * - disable the counter's interrupt generation (each counter has it's
24 * - enable the counter's interrupt generation.
25 * - set the new event type.
30 * ignoring that counter. When re-enabling, we have to reset the value and
104 * The ARM performance counters can count micro DTLB misses, micro ITLB
105 * misses and main TLB misses. There isn't an event for TLB misses, so
106 * use the micro misses here and if users want the main TLB misses they
167 * The ARM performance counters can count micro DTLB misses, micro ITLB
[all …]
/kernel/linux/linux-5.10/arch/arm/kernel/
Dperf_event_v6.c1 // SPDX-License-Identifier: GPL-2.0
17 * - change the counter to count the ETMEXTOUT[0] signal (0x20). This
19 * - disable the counter's interrupt generation (each counter has it's
24 * - enable the counter's interrupt generation.
25 * - set the new event type.
30 * ignoring that counter. When re-enabling, we have to reset the value and
104 * The ARM performance counters can count micro DTLB misses, micro ITLB
105 * misses and main TLB misses. There isn't an event for TLB misses, so
106 * use the micro misses here and if users want the main TLB misses they
167 * The ARM performance counters can count micro DTLB misses, micro ITLB
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/iommu/
Drenesas,ipmmu-vmsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iommu/renesas,ipmmu-vmsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas VMSA-Compatible IOMMU
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 connected to the IPMMU through a port called micro-TLB.
20 - items:
21 - enum:
22 - renesas,ipmmu-r8a73a4 # R-Mobile APE6
[all …]
Dmsm,iommu-v0.txt5 of the CPU, each connected to the IOMMU through a port called micro-TLB.
9 - compatible: Must contain "qcom,apq8064-iommu".
10 - reg: Base address and size of the IOMMU registers.
11 - interrupts: Specifiers for the MMU fault interrupts. For instances that
12 support secure mode two interrupts must be specified, for non-secure and
15 - #iommu-cells: The number of cells needed to specify the stream id. This
17 - qcom,ncb: The total number of context banks in the IOMMU.
18 - clocks : List of clocks to be used during SMMU register access. See
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
21 here, there must be a corresponding entry in clock-names
[all …]
/kernel/linux/linux-5.10/arch/mips/mm/
Dtlb-funcs.S6 * Micro-assembler generated tlb handler functions.
10 * Based on mm/page-funcs.c
12 * Copyright (C) 2012 Ralf Baechle <ralf@linux-mips.org>
/kernel/linux/linux-4.19/arch/mips/mm/
Dtlb-funcs.S6 * Micro-assembler generated tlb handler functions.
10 * Based on mm/page-funcs.c
12 * Copyright (C) 2012 Ralf Baechle <ralf@linux-mips.org>
/kernel/linux/linux-5.10/drivers/edac/
Dmce_amd.c1 // SPDX-License-Identifier: GPL-2.0-only
71 "PFB non-cacheable bit parity error",
101 "Link-defined sync error packets detected on HT link",
151 "Level 1 TLB parity error",
164 "Level 2 TLB parity error",
174 "An ECC error was detected on a data cache read-modify-write by a store",
179 "An ECC error was detected on an EMEM read-modify-write by a store",
180 "A parity error was detected in an L1 TLB entry by any access",
181 "A parity error was detected in an L2 TLB entry by any access",
200 "IC Microtag or Full Tag Multi-hit Error",
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/amd/amdgpu/
Damdgpu_gmc.h2 * Copyright 2018 Advanced Micro Devices, Inc.
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
52 /* flush the vm tlb via mmio */
55 /* flush the vm tlb via ring */
58 /* Change the VMID -> PASID mapping */
116 * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR
125 WARN_ON(gmc->real_vram_size < gmc->visible_vram_size); in amdgpu_gmc_vram_full_visible()
127 return (gmc->real_vram_size == gmc->visible_vram_size); in amdgpu_gmc_vram_full_visible()
/kernel/linux/linux-4.19/arch/powerpc/platforms/8xx/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
33 bool "Embedded Planet EP88xC (a.k.a. CWH-PPC-885XN-VE)"
39 MPC885 Evaluation System and/or the CWH-PPC-885XN-VE.
42 bool "Analogue & Micro Adder 875"
45 This enables support for the Analogue & Micro Adder 875
56 menu "Freescale Ethernet driver platform-specific options"
76 Enable FEC2 to serve as 2-nd Ethernet channel. Note that SMC2
77 (often 2-nd UART) will not work if this is enabled.
83 Enable SCC3 to serve as 2-nd Ethernet channel. Note that SMC1
84 (often 1-nd UART) will not work if this is enabled.
[all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/amdzen2/
Drecommended.json4 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)",
119 "MetricGroup": "tlb"
148 "BriefDescription": "Micro-ops Dispatched",
160 "BriefDescription": "Micro-ops Retired"
168 "ScaleUnit": "3e-5MiB"
172 …roximate: Combined DRAM B/bytes of all channels on a NPS1 node (die) (may need --metric-no-group)",
176 "ScaleUnit": "6.1e-5MiB"
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/amdzen1/
Drecommended.json4 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)",
119 "MetricGroup": "tlb"
148 "BriefDescription": "Micro-ops Dispatched",
160 "BriefDescription": "Micro-ops Retired"
168 "ScaleUnit": "3e-5MiB"
172 …roximate: Combined DRAM B/bytes of all channels on a NPS1 node (die) (may need --metric-no-group)",
176 "ScaleUnit": "6.1e-5MiB"
/kernel/linux/linux-5.10/arch/arc/mm/
Dtlbex.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * TLB Exception Handling for ARC
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
8 * -MMU v1: moved out legacy code into a seperate file
9 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
13 * -For MMU V2, we need not do heuristics at the time of commiting a D-TLB
14 * entry, so that it doesn't knock out it's I-TLB entry
15 * -Some more fine tuning:
19 * -Practically rewrote the I/D TLB Miss handlers
26 * -Passing ECR (Exception Cause REG) to do_page_fault( ) for printing
[all …]
Dtlb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TLB Management (flush/create/diagnostics) for ARC700
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
8 * -Reintroduce duplicate PD fixup - some customer chips still have the issue
11 * -No need to flush_cache_page( ) for each call to update_mmu_cache()
13 * = page-fault thrice as fast (75 usec to 28 usec)
18 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
22 * -MMU v2/v3 BCRs decoded differently
23 * -Remove TLB_SIZE hardcoding as it's variable now: 256 or 512
24 * -tlb_entry_erase( ) can be void
[all …]
/kernel/linux/linux-4.19/arch/arc/include/asm/
Dentry-arcv2.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <asm/asm-offsets.h>
7 #include <asm/irqflags-arcv2.h>
10 /*------------------------------------------------------------------------*/
13 ; Before jumping to Interrupt Vector, hardware micro-ops did following:
14 ; 1. SP auto-switched to kernel mode stack
16 ; 3. Auto saved: r0-r11, blink, LPE,LPS,LPC, JLI,LDI,EI, PC, STAT32
22 st.as r9, [sp, -10] ; save r9 in it's final stack slot
55 ; Saving pt_regs->sp correctly requires some extra work due to the way
57 ; - U mode: retrieve it from AUX_USER_SP
[all …]
/kernel/linux/linux-4.19/arch/arc/mm/
Dtlb.c2 * TLB Management (flush/create/diagnostics) for ARC700
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
11 * -Reintroduce duplicate PD fixup - some customer chips still have the issue
14 * -No need to flush_cache_page( ) for each call to update_mmu_cache()
16 * = page-fault thrice as fast (75 usec to 28 usec)
21 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
25 * -MMU v2/v3 BCRs decoded differently
26 * -Remove TLB_SIZE hardcoding as it's variable now: 256 or 512
27 * -tlb_entry_erase( ) can be void
28 * -local_flush_tlb_range( ):
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
Damdgpu_gmc.h2 * Copyright 2018 Advanced Micro Devices, Inc.
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
111 /* flush the vm tlb via mmio */
114 /* flush the vm tlb via pasid */
117 /* flush the vm tlb via ring */
120 /* Change the VMID -> PASID mapping */
134 /* get the amount of memory used by the vbios for pre-OS console */
144 /* physical node (0-3) */
146 /* number of nodes (0-4) */
245 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((ad…
[all …]
/kernel/linux/linux-5.10/Documentation/firmware-guide/acpi/apei/
Doutput_format.rst1 .. SPDX-License-Identifier: GPL-2.0
55 [cache error][, TLB error][, bus error][, micro-architectural error]
81 unknown | no error | single-bit ECC | multi-bit ECC | \
82 single-symbol chipkill ECC | multi-symbol chipkill ECC | master abort | \
106 downstream switch port | PCIe to PCI/PCI-X bridge | \
107 PCI/PCI-X to PCIe bridge | root complex integrated endpoint device | \
121 Replay Timer Timeout | Advisory Non-Fatal
/kernel/linux/linux-4.19/Documentation/acpi/apei/
Doutput_format.txt52 [cache error][, TLB error][, bus error][, micro-architectural error]
78 unknown | no error | single-bit ECC | multi-bit ECC | \
79 single-symbol chipkill ECC | multi-symbol chipkill ECC | master abort | \
103 downstream switch port | PCIe to PCI/PCI-X bridge | \
104 PCI/PCI-X to PCIe bridge | root complex integrated endpoint device | \
118 Replay Timer Timeout | Advisory Non-Fatal
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdkfd/
Dkfd_crat.h2 * Copyright 2014 Advanced Micro Devices, Inc.
45 #define CRAT_OEMID_64BIT_MASK ((1ULL << (CRAT_OEMID_LENGTH * 8)) - 1)
141 uint8_t reserved2[CRAT_MEMORY_RESERVED_LENGTH - 1];
174 * HSA TLB Affinity structure and definitions
277 uint8_t reserved2[CRAT_IOLINK_RESERVED_LENGTH - 1];
282 * HSA generic sub-type header
/kernel/linux/linux-4.19/drivers/gpu/drm/amd/amdkfd/
Dkfd_crat.h2 * Copyright 2014 Advanced Micro Devices, Inc.
45 #define CRAT_OEMID_64BIT_MASK ((1ULL << (CRAT_OEMID_LENGTH * 8)) - 1)
141 uint8_t reserved2[CRAT_MEMORY_RESERVED_LENGTH - 1];
174 * HSA TLB Affinity structure and definitions
275 * HSA generic sub-type header

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