Searched +full:mmio +full:- +full:sram (Results 1 – 25 of 285) sorted by relevance
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/sram/ |
| D | sram.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sram/sram.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic on-chip SRAM
10 - Rob Herring <robh@kernel.org>
15 Each child of the sram node specifies a region of reserved memory. Each
19 Following the generic-names recommended practice, node names should
25 pattern: "^sram(@.*)?"
30 - mmio-sram
[all …]
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| D | allwinner,sun4i-a10-system-control.yaml | 1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The SRAM controller found on most Allwinner devices is represented
15 by a regular node for the SRAM controller itself, with sub-nodes
16 representing the SRAM handled by the SRAM controller.
19 "#address-cells":
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/sram/ |
| D | rockchip-smp-sram.txt | 1 Rockchip SRAM for smp bringup:
2 ------------------------------
4 Rockchip's smp-capable SoCs use the first part of the sram for the bringup
6 residing at the very beginning of the sram.
8 Therefore a reserved section sub-node has to be added to the mmio-sram
11 Required sub-node properties:
12 - compatible : should be "rockchip,rk3066-smp-sram"
14 The rest of the properties should follow the generic mmio-sram discription
15 found in Documentation/devicetree/bindings/sram/sram.txt
19 sram: sram@10080000 {
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| D | sunxi-sram.txt | 1 Allwinnner SoC SRAM controllers
2 -----------------------------------------------------
4 The SRAM controller found on most Allwinner devices is represented by
5 a regular node for the SRAM controller itself, with sub-nodes
6 reprensenting the SRAM handled by the SRAM controller.
9 ---------------
12 - compatible : should be:
13 - "allwinner,sun4i-a10-sram-controller" (deprecated)
14 - "allwinner,sun4i-a10-system-control"
15 - "allwinner,sun5i-a13-system-control"
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| D | renesas,smp-sram.txt | 1 * Renesas SMP SRAM
3 Renesas R-Car Gen2 and RZ/G1 SoCs need a small piece of SRAM for the jump stub
5 This memory is reserved by adding a child node to a "mmio-sram" node, cfr.
6 Documentation/devicetree/bindings/sram/sram.txt.
9 - compatible: Must be "renesas,smp-sram",
10 - reg: Address and length of the reserved SRAM.
16 icram1: sram@e63c0000 {
17 compatible = "mmio-sram";
19 #address-cells = <1>;
20 #size-cells = <1>;
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| D | samsung-sram.txt | 2 ------------------------------------
4 Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup
8 Therefore reserved section sub-nodes have to be added to the mmio-sram
10 non-secure execution environment.
12 Required sub-node properties:
13 - compatible : depending upon boot mode, should be
14 "samsung,exynos4210-sysram" : for Secure SYSRAM
15 "samsung,exynos4210-sysram-ns" : for Non-secure SYSRAM
17 The rest of the properties should follow the generic mmio-sram discription
18 found in Documentation/devicetree/bindings/sram/sram.txt
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| D | sram.txt | 1 Generic on-chip SRAM
7 - compatible : mmio-sram or atmel,sama5d2-securam
9 - reg : SRAM iomem address range
11 Reserving sram areas:
12 ---------------------
14 Each child of the sram node specifies a region of reserved memory. Each
18 Following the generic-names recommended practice, node names should
22 Required properties in the sram node:
24 - #address-cells, #size-cells : should use the same values as the root node
25 - ranges : standard definition, should translate from local addresses
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| D | rockchip-pmu-sram.txt | 1 Rockchip SRAM for pmu:
2 ------------------------------
4 The sram of pmu is used to store the function of resume from maskrom(the 1st
5 level loader). This is a common use of the "pmu-sram" because it keeps power
9 - compatible : should be "rockchip,rk3288-pmu-sram"
10 - reg : physical base address and the size of the registers window
13 sram@ff720000 {
14 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/amlogic/ |
| D | smp-sram.txt | 1 Amlogic Meson8 and Meson8b SRAM for smp bringup:
2 ------------------------------------------------
4 Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
8 Therefore a reserved section sub-node has to be added to the mmio-sram
11 Required sub-node properties:
12 - compatible : depending on the SoC this should be one of:
13 "amlogic,meson8-smp-sram"
14 "amlogic,meson8b-smp-sram"
16 The rest of the properties should follow the generic mmio-sram discription
17 found in ../../misc/sram.txt
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/sunxi/ |
| D | smp-sram.txt | 1 Allwinner SRAM for smp bringup:
2 ------------------------------------------------
4 Allwinner's A80 SoC uses part of the secure sram for hotplugging of the
9 Therefore a reserved section sub-node has to be added to the mmio-sram
12 Note that this is separate from the Allwinner SRAM controller found in
13 ../../sram/sunxi-sram.txt. This SRAM is secure only and not mappable to
16 Also there are no "secure-only" properties. The implementation should
17 check if this SRAM is usable first.
19 Required sub-node properties:
20 - compatible : depending on the SoC this should be one of:
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | lpc4350.dtsi | 9 * Released under the terms of 3-clause BSD License
19 compatible = "arm,cortex-m4";
24 sram0: sram@10000000 {
25 compatible = "mmio-sram";
26 reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */
29 sram1: sram@10080000 {
30 compatible = "mmio-sram";
31 reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */
34 sram2: sram@20000000 {
35 compatible = "mmio-sram";
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| D | lpc4357.dtsi | 9 * Released under the terms of 3-clause BSD License
19 compatible = "arm,cortex-m4";
24 sram0: sram@10000000 {
25 compatible = "mmio-sram";
26 reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */
29 sram1: sram@10080000 {
30 compatible = "mmio-sram";
31 reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */
34 sram2: sram@20000000 {
35 compatible = "mmio-sram";
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| D | imx6qp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
9 ocram2: sram@940000 {
10 compatible = "mmio-sram";
15 ocram3: sram@960000 {
16 compatible = "mmio-sram";
21 aips-bus@2100000 {
23 compatible = "fsl,imx6qp-pre";
27 clock-names = "axi";
32 compatible = "fsl,imx6qp-pre";
36 clock-names = "axi";
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| D | r8a77470.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a77470-cpg-mssr.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
24 clock-frequency = <1000000000>;
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | lpc4350.dtsi | 9 * Released under the terms of 3-clause BSD License
19 compatible = "arm,cortex-m4";
24 sram0: sram@10000000 {
25 compatible = "mmio-sram";
26 reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */
29 sram1: sram@10080000 {
30 compatible = "mmio-sram";
31 reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */
34 sram2: sram@20000000 {
35 compatible = "mmio-sram";
[all …]
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| D | lpc4357.dtsi | 9 * Released under the terms of 3-clause BSD License
19 compatible = "arm,cortex-m4";
24 sram0: sram@10000000 {
25 compatible = "mmio-sram";
26 reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */
29 sram1: sram@10080000 {
30 compatible = "mmio-sram";
31 reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */
34 sram2: sram@20000000 {
35 compatible = "mmio-sram";
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| D | imx6qp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
9 ocram2: sram@940000 {
10 compatible = "mmio-sram";
15 ocram3: sram@960000 {
16 compatible = "mmio-sram";
23 compatible = "fsl,imx6qp-pre";
27 clock-names = "axi";
32 compatible = "fsl,imx6qp-pre";
36 clock-names = "axi";
41 compatible = "fsl,imx6qp-pre";
[all …]
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| D | at91sam9xe.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * at91sam9xe.dtsi - Device Tree Include file for AT91SAM9XE family SoC
6 * 2015 Alexandre Belloni <alexandre.Belloni@free-electrons.com>
15 sram0: sram@2ff000 {
19 sram1: sram@300000 {
20 compatible = "mmio-sram";
22 #address-cells = <1>;
23 #size-cells = <1>;
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| D | at91sam9g20.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC
5 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
18 sram0: sram@2ff000 {
22 sram1: sram@2fc000 {
23 compatible = "mmio-sram";
25 #address-cells = <1>;
26 #size-cells = <1>;
33 compatible = "atmel,at91sam9g20-i2c";
37 compatible = "atmel,at91sam9rl-ssc";
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/ |
| D | arm,scmi.txt | 2 ----------------------------------------------------------
17 - compatible : shall be "arm,scmi"
18 - mboxes: List of phandle and mailbox channel specifiers. It should contain
22 - shmem : List of phandle pointing to the shared memory(SHM) area as per
24 - #address-cells : should be '1' if the device has sub-nodes, maps to
25 protocol identifier for a given sub-node.
26 - #size-cells : should be '0' as 'reg' property doesn't have any size
31 - mbox-names: shall be "tx" or "rx" depending on mboxes entries.
40 Each protocol supported shall have a sub-node with corresponding compatible
43 mboxes, mbox-names and shmem shall be present in the sub-node corresponding
[all …]
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| D | arm,scpi.txt | 2 ----------------------------------------------------------
10 - compatible : should be
12 * "arm,scpi-pre-1.0" : For implementations complying to all
14 - mboxes: List of phandle and mailbox channel specifiers
17 - shmem : List of phandle pointing to the shared memory(SHM) area between the
27 ------------------------------------------------------------
34 - compatible : should be "arm,scpi-clocks"
36 protocol much be listed as sub-nodes under this node.
38 Sub-nodes
41 - compatible : shall include one of the following
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | arm,scmi.txt | 2 ----------------------------------------------------------
17 - compatible : shall be "arm,scmi" or "arm,scmi-smc" for smc/hvc transports
18 - mboxes: List of phandle and mailbox channel specifiers. It should contain
22 - shmem : List of phandle pointing to the shared memory(SHM) area as per
24 - #address-cells : should be '1' if the device has sub-nodes, maps to
25 protocol identifier for a given sub-node.
26 - #size-cells : should be '0' as 'reg' property doesn't have any size
28 - arm,smc-id : SMC id required when using smc or hvc transports
32 - mbox-names: shall be "tx" or "rx" depending on mboxes entries.
41 Each protocol supported shall have a sub-node with corresponding compatible
[all …]
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| D | arm,scpi.txt | 2 ----------------------------------------------------------
10 - compatible : should be
12 * "arm,scpi-pre-1.0" : For implementations complying to all
14 - mboxes: List of phandle and mailbox channel specifiers
17 - shmem : List of phandle pointing to the shared memory(SHM) area between the
27 ------------------------------------------------------------
34 - compatible : should be "arm,scpi-clocks"
36 protocol much be listed as sub-nodes under this node.
38 Sub-nodes
41 - compatible : shall include one of the following
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mailbox/ |
| D | mailbox.txt | 9 - #mbox-cells: Must be at least 1. Number of cells in a mailbox
15 #mbox-cells = <1>;
22 - mboxes: List of phandle and mailbox channel specifiers.
25 - mbox-names: List of identifier strings for each mailbox channel.
26 - shmem : List of phandle pointing to the shared memory(SHM) area between the
35 mbox-names = "pwr-ctrl", "rpc";
41 sram: sram@50000000 {
42 compatible = "mmio-sram";
45 #address-cells = <1>;
46 #size-cells = <1>;
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/mailbox/ |
| D | mailbox.txt | 9 - #mbox-cells: Must be at least 1. Number of cells in a mailbox
15 #mbox-cells = <1>;
22 - mboxes: List of phandle and mailbox channel specifiers.
25 - mbox-names: List of identifier strings for each mailbox channel.
26 - shmem : List of phandle pointing to the shared memory(SHM) area between the
35 mbox-names = "pwr-ctrl", "rpc";
41 sram: sram@50000000 {
42 compatible = "mmio-sram";
45 #address-cells = <1>;
46 #size-cells = <1>;
[all …]
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