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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Dmrvl,intc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mrvl,intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thomas Gleixner <tglx@linutronix.de>
11 - Jason Cooper <jason@lakedaemon.net>
12 - Marc Zyngier <maz@kernel.org>
13 - Rob Herring <robh+dt@kernel.org>
16 - if:
21 const: marvell,orion-intc
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/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dmmp2.dtsi11 #include <dt-bindings/clock/marvell,mmp2.h>
24 #address-cells = <1>;
25 #size-cells = <1>;
26 compatible = "simple-bus";
27 interrupt-parent = <&intc>;
30 L2: l2-cache {
31 compatible = "marvell,tauros2-cache";
32 marvell,tauros2-cache-features = <0x3>;
36 compatible = "mrvl,axi-bus", "simple-bus";
37 #address-cells = <1>;
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dmmp3.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/marvell,mmp2.h>
7 #include <dt-bindings/power/marvell,mmp2.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
17 enable-method = "marvell,mmp3-smp";
22 next-level-cache = <&l2>;
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Dmmp2.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/marvell,mmp2.h>
8 #include <dt-bindings/power/marvell,mmp2.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
24 #address-cells = <1>;
25 #size-cells = <1>;
26 compatible = "simple-bus";
27 interrupt-parent = <&intc>;
30 L2: l2-cache {
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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/interrupt-controller/
Dmrvl,intc.txt4 - compatible : Should be "mrvl,mmp-intc", "mrvl,mmp2-intc" or
5 "mrvl,mmp2-mux-intc"
6 - reg : Address and length of the register set of the interrupt controller.
7 If the interrupt controller is intc, address and length means the range
8 of the whold interrupt controller. If the interrupt controller is mux-intc,
9 address and length means one register. Since address of mux-intc is in the
10 range of intc. mux-intc is secondary interrupt controller.
11 - reg-names : Name of the register set of the interrupt controller. It's
12 only required in mux-intc interrupt controller.
13 - interrupts : Should be the port interrupt shared by mux interrupts. It's
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/kernel/linux/linux-5.10/drivers/irqchip/
Dirq-mmp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-mmp/irq.c
6 * Copyright (C) 2008 - 2012 Marvell Technology Group Ltd.
69 struct irq_domain *domain = d->domain; in icu_mask_ack_irq()
70 struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data; in icu_mask_ack_irq()
74 hwirq = d->irq - data->virq_base; in icu_mask_ack_irq()
77 r &= ~data->conf_mask; in icu_mask_ack_irq()
78 r |= data->conf_disable; in icu_mask_ack_irq()
82 if ((data->virq_base == data->clr_mfp_irq_base) in icu_mask_ack_irq()
83 && (hwirq == data->clr_mfp_hwirq)) in icu_mask_ack_irq()
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/kernel/linux/linux-4.19/drivers/irqchip/
Dirq-mmp.c2 * linux/arch/arm/mach-mmp/irq.c
5 * Copyright (C) 2008 - 2012 Marvell Technology Group Ltd.
68 struct irq_domain *domain = d->domain; in icu_mask_ack_irq()
69 struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data; in icu_mask_ack_irq()
73 hwirq = d->irq - data->virq_base; in icu_mask_ack_irq()
76 r &= ~data->conf_mask; in icu_mask_ack_irq()
77 r |= data->conf_disable; in icu_mask_ack_irq()
81 if ((data->virq_base == data->clr_mfp_irq_base) in icu_mask_ack_irq()
82 && (hwirq == data->clr_mfp_hwirq)) in icu_mask_ack_irq()
85 r = readl_relaxed(data->reg_mask) | (1 << hwirq); in icu_mask_ack_irq()
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