Home
last modified time | relevance | path

Searched +full:mode +full:- +full:flag (Results 1 – 25 of 1075) sorted by relevance

12345678910>>...43

/kernel/linux/linux-4.19/include/linux/
Dkbd_kern.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 * kbd->xxx contains the VC-local things (flag settings etc..)
28 /* 8 modifiers - the names do not have any meaning at all;
30 #define VC_SHIFTLOCK KG_SHIFT /* shift lock mode */
31 #define VC_ALTGRLOCK KG_ALTGR /* altgr lock mode */
32 #define VC_CTRLLOCK KG_CTRL /* control lock mode */
33 #define VC_ALTLOCK KG_ALT /* alt lock mode */
34 #define VC_SHIFTLLOCK KG_SHIFTL /* shiftl lock mode */
35 #define VC_SHIFTRLOCK KG_SHIFTR /* shiftr lock mode */
36 #define VC_CTRLLLOCK KG_CTRLL /* ctrll lock mode */
[all …]
/kernel/linux/linux-5.10/include/linux/
Dkbd_kern.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 * kbd->xxx contains the VC-local things (flag settings etc..)
28 /* 8 modifiers - the names do not have any meaning at all;
30 #define VC_SHIFTLOCK KG_SHIFT /* shift lock mode */
31 #define VC_ALTGRLOCK KG_ALTGR /* altgr lock mode */
32 #define VC_CTRLLOCK KG_CTRL /* control lock mode */
33 #define VC_ALTLOCK KG_ALT /* alt lock mode */
34 #define VC_SHIFTLLOCK KG_SHIFTL /* shiftl lock mode */
35 #define VC_SHIFTRLOCK KG_SHIFTR /* shiftr lock mode */
36 #define VC_CTRLLLOCK KG_CTRLL /* ctrll lock mode */
[all …]
/kernel/liteos_m/targets/riscv_nuclei_gd32vf103_soc_gcc/SoC/gd32vf103/Common/Source/Drivers/
Dgd32vf103_i2c.c5 \version 2019-6-5, V1.0.0, firmware for GD32VF103
40 #define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU) /*!< i2c flag mask */
74 …\param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 40…
75 \param[in] dutycyc: duty cycle in fast mode
100 /* the maximum SCL rise time is 1000ns in standard mode */ in i2c_clock_config()
111 /* the CLKC in standard mode minmum value is 4 */ in i2c_clock_config()
117 /* the maximum SCL rise time is 300ns in fast mode */ in i2c_clock_config()
130 /* the CLKC in fast mode minmum value is 1 */ in i2c_clock_config()
142 \param[in] mode:
144 \arg I2C_I2CMODE_ENABLE: I2C mode
[all …]
Dgd32vf103_can.c5 \version 2019-6-5, V1.0.0, firmware for GD32VF103
77 ((can_parameter_struct*)p_struct)->auto_bus_off_recovery = DISABLE; in can_struct_para_init()
78 ((can_parameter_struct*)p_struct)->no_auto_retrans = DISABLE; in can_struct_para_init()
79 ((can_parameter_struct*)p_struct)->auto_wake_up = DISABLE; in can_struct_para_init()
80 ((can_parameter_struct*)p_struct)->prescaler = 0x03FFU; in can_struct_para_init()
81 ((can_parameter_struct*)p_struct)->rec_fifo_overwrite = DISABLE; in can_struct_para_init()
82 ((can_parameter_struct*)p_struct)->resync_jump_width = CAN_BT_SJW_1TQ; in can_struct_para_init()
83 ((can_parameter_struct*)p_struct)->time_segment_1 = CAN_BT_BS1_3TQ; in can_struct_para_init()
84 ((can_parameter_struct*)p_struct)->time_segment_2 = CAN_BT_BS2_1TQ; in can_struct_para_init()
85 ((can_parameter_struct*)p_struct)->time_triggered = DISABLE; in can_struct_para_init()
[all …]
Dgd32vf103_usart.c5 \version 2019-6-5, V1.0.0, firmware for GD32VF103
133 /* configure USART parity mode */ in usart_parity_config()
214 /* configure transfer mode */ in usart_transmit_config()
235 /* configure receiver mode */ in usart_receive_config()
263 \brief configure the address of the USART in wake up by address match mode
276 \brief receiver in mute mode
287 \brief receiver in active mode
298 \brief configure wakeup method in mute mode
300 \param[in] wmethod: two methods be used to enter or exit the mute mode
314 \brief enable LIN mode
[all …]
Dgd32vf103_pmu.c5 \version 2019-6-5, V1.0.0, firmware for GD32VF103
90 \brief PMU work at sleep mode
100 /* clear sleepdeep bit of RISC-V system control register */ in pmu_to_sleepmode()
103 /* select WFI or WFE command to enter sleep mode */ in pmu_to_sleepmode()
114 \brief PMU work at deepsleep mode
117 \arg PMU_LDO_NORMAL: LDO work at normal power mode when pmu enter deepsleep mode
118 \arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode
132 /* set CSR_SLEEPVALUE bit of RISC-V system control register */ in pmu_to_deepsleepmode()
134 /* select WFI or WFE command to enter deepsleep mode */ in pmu_to_deepsleepmode()
142 /* reset sleepdeep bit of RISC-V system control register */ in pmu_to_deepsleepmode()
[all …]
Dgd32vf103_spi.c5 \version 2019-6-5, V1.0.0, firmware for GD32VF103
90 spi_struct->device_mode = SPI_SLAVE; in spi_struct_para_init()
91 spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX; in spi_struct_para_init()
92 spi_struct->frame_size = SPI_FRAMESIZE_8BIT; in spi_struct_para_init()
93 spi_struct->nss = SPI_NSS_HARD; in spi_struct_para_init()
94 spi_struct->clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; in spi_struct_para_init()
95 spi_struct->prescale = SPI_PSC_2; in spi_struct_para_init()
122 reg |= spi_struct->device_mode; in spi_init()
123 /* select SPI transfer mode */ in spi_init()
124 reg |= spi_struct->trans_mode; in spi_init()
[all …]
Dgd32vf103_adc.c5 \version 2019-6-5, V1.0.0, firmware for GD32VF103
38 /* discontinuous mode macro*/
85 \brief configure the ADC sync mode
87 \param[in] mode: ADC mode
90 …ARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined regular parallel + inserted parallel mode
91 …PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined regular parallel + trigger rotation mode
92 …ALLEL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode
93 …ALLEL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode
94 \arg ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode only
95 \arg ADC_DAUL_REGULAL_PARALLEL: ADC0 and ADC1 work in regular parallel mode only
[all …]
/kernel/liteos_m/targets/riscv_nuclei_gd32vf103_soc_gcc/SoC/gd32vf103/Common/Include/
Dgd32vf103_i2c.h5 \version 2019-6-5, V1.0.0, firmware for GD32VF103
60 #define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */
65 #define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */
83 #define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */
84 #define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit addr…
85 #define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */
86 #define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */
89 #define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */
90 …DDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */
93 #define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */
[all …]
Dgd32vf103_spi.h5 \version 2019-6-5, V1.0.0, firmware for GD32VF103
62 #define SPI_CTL0_MSTMOD BIT(2) /*!< master mode en…
65 #define SPI_CTL0_LF BIT(7) /*!< LSB first mode…
66 … BIT(8) /*!< NSS pin selection in NSS software mode */
67 …_SWNSSEN BIT(9) /*!< NSS software mode selection */
79 …L1_NSSP BIT(3) /*!< SPI NSS pulse mode enable */
80 #define SPI_CTL1_TMOD BIT(4) /*!< SPI TI mode en…
93 …AT_TRANS BIT(7) /*!< transmitting on-going bit */
113 …PCMSMOD BIT(7) /*!< PCM frame synchronization mode */
114 … SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */
[all …]
Dgd32vf103_pmu.h5 \version 2019-6-5, V1.0.0, firmware for GD32VF103
51 #define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */
52 #define PMU_CTL_STBMOD BIT(1) /*!< standby mode */
53 #define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */
54 #define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */
60 #define PMU_CS_WUF BIT(0) /*!< wakeup flag */
61 #define PMU_CS_STBF BIT(1) /*!< standby flag */
62 …ine PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */
77 /* PMU flag definitions */
78 #define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */
[all …]
Dgd32vf103_usart.h5 \version 2019-6-5, V1.0.0, firmware for GD32VF103
60 #define USART_STAT_PERR BIT(0) /*!< parity error flag */
61 #define USART_STAT_FERR BIT(1) /*!< frame error flag */
62 #define USART_STAT_NERR BIT(2) /*!< noise error flag */
64 …ne USART_STAT_IDLEF BIT(4) /*!< IDLE frame detected flag */
68 …ine USART_STAT_LBDF BIT(8) /*!< LIN break detected flag */
69 #define USART_STAT_CTSF BIT(9) /*!< CTS change flag */
75 #define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-…
76 #define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-r…
80 …RT_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */
[all …]
Dgd32vf103_dma.h5 \version 2019-6-5, V1.0.0, firmware for GD32VF103
48 #define DMA_INTF(dmax) REG32((dmax) + 0x00U) /*!< DMA interrupt flag register */
49 #define DMA_INTC(dmax) REG32((dmax) + 0x04U) /*!< DMA interrupt flag clear regi…
88 #define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of chann…
89 #define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of c…
90 #define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of c…
91 #define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */
94 #define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of…
95 #define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of …
96 …C_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */
[all …]
Dgd32vf103_timer.h5 \version 2019-6-5, V1.0.0, firmware for GD32VF103
54 #define TIMER_SMCFG(timerx) REG32((timerx) + 0x08U) /*!< TIMER slave mode co…
56 …_INTF(timerx) REG32((timerx) + 0x10U) /*!< TIMER interrupt flag register */
78 #define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */
80 #define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */
81 #define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */
88 #define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */
89 … BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */
99 #define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */
101 #define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */
[all …]
Dgd32vf103_rtc.h5 \version 2019-6-5, V1.0.0, firmware for GD32VF103
64 #define RTC_CTL_SCIF BIT(0) /*!< second interrupt flag */
65 #define RTC_CTL_ALRMIF BIT(1) /*!< alarm interrupt flag */
66 #define RTC_CTL_OVIF BIT(2) /*!< overflow interrupt flag */
67 #define RTC_CTL_RSYNF BIT(3) /*!< registers synchronized flag */
68 #define RTC_CTL_CMF BIT(4) /*!< configuration mode flag */
69 …ne RTC_CTL_LWOFF BIT(5) /*!< last write operation finished flag */
101 /* RTC interrupt flag definitions */
102 #define RTC_INT_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */
103 #define RTC_INT_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/
Dmmc-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
25 "#address-cells":
30 "#size-cells":
37 broken-cd:
38 $ref: /schemas/types.yaml#/definitions/flag
42 cd-gpios:
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dethernet-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24 - $nodename
[all …]
/kernel/linux/linux-4.19/Documentation/ioctl/
Dhdio.txt9 the HD/IDE layer. These are by-and-large implemented (as of Linux 2.6)
20 HDIO_GET_QDMA get use-qdma flag
23 HDIO_GET_KEEPSETTINGS get keep-settings-on-reset flag
25 HDIO_GET_NOWERR get ignore-write-error flag
26 HDIO_GET_DMA get use-dma flag
29 HDIO_GET_WCACHE get write cache mode on|off
31 HDIO_GET_ADDRESS get sector addressing mode
40 ioctls that pass non-pointer values:
46 HDIO_SET_NOWERR change ignore-write-error flag
47 HDIO_SET_DMA change use-dma flag
[all …]
/kernel/linux/linux-5.10/Documentation/admin-guide/mm/
Dnuma_memory_policy.rst12 supported platforms with Non-Uniform Memory Access architectures since 2.4.?.
18 (``Documentation/admin-guide/cgroup-v1/cpusets.rst``)
21 programming interface that a NUMA-aware application can take advantage of. When
30 ------------------------
43 not to overload the initial boot node with boot-time
47 this is an optional, per-task policy. When defined for a
56 [clone() w/o the CLONE_VM flag] and exec*(). This allows a parent task
63 In a multi-threaded task, task policies apply only to the thread
95 mmap()ed with the MAP_ANONYMOUS flag. If a VMA policy is
97 used the MAP_SHARED flag. If the file mapping used the
[all …]
/kernel/linux/linux-4.19/Documentation/admin-guide/mm/
Dnuma_memory_policy.rst12 supported platforms with Non-Uniform Memory Access architectures since 2.4.?.
18 (``Documentation/cgroup-v1/cpusets.txt``)
21 programming interface that a NUMA-aware application can take advantage of. When
30 ------------------------
43 not to overload the initial boot node with boot-time
47 this is an optional, per-task policy. When defined for a
56 [clone() w/o the CLONE_VM flag] and exec*(). This allows a parent task
63 In a multi-threaded task, task policies apply only to the thread
95 mmap()ed with the MAP_ANONYMOUS flag. If a VMA policy is
97 used the MAP_SHARED flag. If the file mapping used the
[all …]
/kernel/linux/linux-5.10/arch/arm/include/asm/
Dvirt.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * Flag indicating that the kernel was not entered in the same mode on every
14 * architecturally defined flag bit here.
23 * __boot_cpu_mode records what mode the primary CPU was booted in.
24 * A correctly-implemented bootloader must start all CPUs in the same mode:
25 * if it fails to do this, the flag BOOT_CPU_MODE_MISMATCH is set to indicate
26 * that some CPU(s) were booted in a different mode.
28 * This allows the kernel to flag an error when the secondaries have come up.
50 /* Reports the availability of HYP mode */
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/
Dspi-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
15 controller may be described for use in SPI master mode or in SPI slave mode,
20 pattern: "^spi(@.*|-[0-9a-f])*$"
22 "#address-cells":
25 "#size-cells":
28 cs-gpios:
[all …]
/kernel/linux/linux-4.19/drivers/isdn/hisax/
Djade.c28 cs->BC_Write_Reg(cs, -1, 0x50, 0x19); in JadeVersion()
31 ver = cs->BC_Read_Reg(cs, -1, 0x60); in JadeVersion()
32 to--; in JadeVersion()
43 ver = cs->BC_Read_Reg(cs, -1, 0x60); in JadeVersion()
56 cs->BC_Write_Reg(cs, -1, COMM_JADE + 1, value); in jade_write_indirect()
58 cs->BC_Write_Reg(cs, -1, COMM_JADE, reg); in jade_write_indirect()
63 ret = cs->BC_Read_Reg(cs, -1, COMM_JADE); in jade_write_indirect()
64 to--; in jade_write_indirect()
78 modejade(struct BCState *bcs, int mode, int bc) in modejade() argument
80 struct IsdnCardState *cs = bcs->cs; in modejade()
[all …]
Dhscx.c30 verA = cs->BC_Read_Reg(cs, 0, HSCX_VSTR) & 0xf; in HscxVersion()
31 verB = cs->BC_Read_Reg(cs, 1, HSCX_VSTR) & 0xf; in HscxVersion()
41 modehscx(struct BCState *bcs, int mode, int bc) in modehscx() argument
43 struct IsdnCardState *cs = bcs->cs; in modehscx()
44 int hscx = bcs->hw.hscx.hscx; in modehscx()
46 if (cs->debug & L1_DEB_HSCX) in modehscx()
47 debugl1(cs, "hscx %c mode %d ichan %d", in modehscx()
48 'A' + hscx, mode, bc); in modehscx()
49 bcs->mode = mode; in modehscx()
50 bcs->channel = bc; in modehscx()
[all …]
/kernel/linux/linux-4.19/drivers/spi/
Dspi-lantiq-ssc.c2 * Copyright (C) 2011-2015 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
3 * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
59 #define LTQ_SPI_CLC_SMC_S 16 /* Clock divider for sleep mode */
61 #define LTQ_SPI_CLC_RMC_S 8 /* Clock divider for normal run mode */
78 #define LTQ_SPI_CON_EM BIT(24) /* Echo mode */
95 #define LTQ_SPI_STAT_BSY BIT(13) /* Busy flag */
96 #define LTQ_SPI_STAT_RUE BIT(12) /* Receive underflow error flag */
97 #define LTQ_SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */
98 #define LTQ_SPI_STAT_AE BIT(10) /* Abort error flag */
99 #define LTQ_SPI_STAT_RE BIT(9) /* Receive error flag */
[all …]

12345678910>>...43