| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | pci-msi.txt | 2 relationship between PCI devices and MSI controllers.
18 Requester ID. A mechanism is required to associate a device with both the MSI
22 For generic MSI bindings, see
23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
30 -------------------
32 - msi-map: Maps a Requester ID to an MSI controller and associated
33 msi-specifier data. The property is an arbitrary number of tuples of
34 (rid-base,msi-controller,msi-base,length), where:
36 * rid-base is a single cell describing the first RID matched by the entry.
38 * msi-controller is a single phandle to an MSI controller
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| D | brcm,iproc-pcie.txt | 4 - compatible:
5 "brcm,iproc-pcie" for the first generation of PAXB based controller,
7 "brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based
9 "brcm,iproc-pcie-paxc" for the first generation of PAXC based
11 "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based
13 PAXB-based root complex is used for external endpoint devices. PAXC-based
15 - reg: base address and length of the PCIe controller I/O register space
16 - #interrupt-cells: set to <1>
17 - interrupt-map-mask and interrupt-map, standard PCI properties to define the
19 - linux,pci-domain: PCI domain ID. Should be unique for each host controller
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| D | brcm,stb-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
15 - enum:
16 - brcm,bcm2711-pcie # The Raspberry Pi 4
17 - brcm,bcm7211-pcie # Broadcom STB version of RPi4
18 - brcm,bcm7278-pcie # Broadcom 7278 Arm
19 - brcm,bcm7216-pcie # Broadcom 7216 Arm
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| D | xilinx-versal-cpm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
17 const: xlnx,versal-cpm-host-1.00
21 - description: Configuration space region and bridge registers.
22 - description: CPM system level control and status registers.
24 reg-names:
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| D | aardvark-pci.txt | 8 - compatible: Should be "marvell,armada-3700-pcie"
9 - reg: range of registers for the PCIe controller
10 - interrupts: the interrupt line of the PCIe controller
11 - #address-cells: set to <3>
12 - #size-cells: set to <2>
13 - device_type: set to "pci"
14 - ranges: ranges for the PCI memory and I/O regions
15 - #interrupt-cells: set to <1>
16 - msi-controller: indicates that the PCIe controller can itself
17 handle MSI interrupts
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| D | xilinx-nwl-pcie.txt | 4 - compatible: Should contain "xlnx,nwl-pcie-2.11"
5 - #address-cells: Address representation for root ports, set to <3>
6 - #size-cells: Size representation for root ports, set to <2>
7 - #interrupt-cells: specifies the number of cells needed to encode an
9 - reg: Should contain Bridge, PCIe Controller registers location,
11 - reg-names: Must include the following entries:
15 - device_type: must be "pci"
16 - interrupts: Should contain NWL PCIe interrupt
17 - interrupt-names: Must include the following entries:
18 "msi1, msi0": interrupt asserted when an MSI is received
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| D | xgene-pci-msi.txt | 1 * AppliedMicro X-Gene v1 PCIe MSI controller
5 - compatible: should be "apm,xgene1-msi" to identify
6 X-Gene v1 PCIe MSI controller block.
7 - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
8 - reg: physical base address (0x79000000) and length (0x900000) for controller
9 registers. These registers include the MSI termination address and data
10 registers as well as the MSI interrupt status registers.
11 - reg-names: not required
12 - interrupts: A list of 16 interrupt outputs of the controller, starting from
14 - interrupt-names: not required
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| D | layerscape-pcie-gen4.txt | 4 the common properties defined in mobiveil-pcie.txt.
7 - compatible: should contain the platform identifier such as:
8 "fsl,lx2160a-pcie"
9 - reg: base addresses and lengths of the PCIe controller register blocks.
12 - interrupts: A list of interrupt outputs of the controller. Must contain an
13 entry for each entry in the interrupt-names property.
14 - interrupt-names: It could include the following entries:
17 none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
19 none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
20 - dma-coherent: Indicates that the hardware IP block can ensure the coherency
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/pci/ |
| D | pci-msi.txt | 2 relationship between PCI devices and MSI controllers.
18 Requester ID. A mechanism is required to associate a device with both the MSI
22 For generic MSI bindings, see
23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
30 -------------------
32 - msi-map: Maps a Requester ID to an MSI controller and associated
33 msi-specifier data. The property is an arbitrary number of tuples of
34 (rid-base,msi-controller,msi-base,length), where:
36 * rid-base is a single cell describing the first RID matched by the entry.
38 * msi-controller is a single phandle to an MSI controller
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| D | brcm,iproc-pcie.txt | 4 - compatible:
5 "brcm,iproc-pcie" for the first generation of PAXB based controller,
7 "brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based
9 "brcm,iproc-pcie-paxc" for the first generation of PAXC based
11 "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based
13 PAXB-based root complex is used for external endpoint devices. PAXC-based
15 - reg: base address and length of the PCIe controller I/O register space
16 - #interrupt-cells: set to <1>
17 - interrupt-map-mask and interrupt-map, standard PCI properties to define the
19 - linux,pci-domain: PCI domain ID. Should be unique for each host controller
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| D | aardvark-pci.txt | 8 - compatible: Should be "marvell,armada-3700-pcie"
9 - reg: range of registers for the PCIe controller
10 - interrupts: the interrupt line of the PCIe controller
11 - #address-cells: set to <3>
12 - #size-cells: set to <2>
13 - device_type: set to "pci"
14 - ranges: ranges for the PCI memory and I/O regions
15 - #interrupt-cells: set to <1>
16 - msi-controller: indicates that the PCIe controller can itself
17 handle MSI interrupts
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| D | xilinx-nwl-pcie.txt | 4 - compatible: Should contain "xlnx,nwl-pcie-2.11"
5 - #address-cells: Address representation for root ports, set to <3>
6 - #size-cells: Size representation for root ports, set to <2>
7 - #interrupt-cells: specifies the number of cells needed to encode an
9 - reg: Should contain Bridge, PCIe Controller registers location,
11 - reg-names: Must include the following entries:
15 - device_type: must be "pci"
16 - interrupts: Should contain NWL PCIe interrupt
17 - interrupt-names: Must include the following entries:
18 "msi1, msi0": interrupt asserted when an MSI is received
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| D | xgene-pci-msi.txt | 1 * AppliedMicro X-Gene v1 PCIe MSI controller
5 - compatible: should be "apm,xgene1-msi" to identify
6 X-Gene v1 PCIe MSI controller block.
7 - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
8 - reg: physical base address (0x79000000) and length (0x900000) for controller
9 registers. These registers include the MSI termination address and data
10 registers as well as the MSI interrupt status registers.
11 - reg-names: not required
12 - interrupts: A list of 16 interrupt outputs of the controller, starting from
14 - interrupt-names: not required
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| D | hisilicon-pcie.txt | 6 Documentation/devicetree/bindings/pci/designware-pcie.txt.
11 - compatible: Should contain "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie".
12 - reg: Should contain rc_dbi, config registers location and length.
13 - reg-names: Must include the following entries:
16 - msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts.
17 - port-id: Should be 0, 1, 2 or 3.
20 - status: Either "ok" or "disabled".
21 - dma-coherent: Present if DMA operations are coherent.
25 compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
27 reg-names = "rc_dbi", "config";
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| D | rockchip-pcie-host.txt | 4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
14 See ../clocks/clock-bindings.txt for details.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/misc/ |
| D | fsl,qoriq-mc.txt | 3 The Freescale Management Complex (fsl-mc) is a hardware resource
5 network-oriented packet processing applications. After the fsl-mc
12 For an overview of the DPAA2 architecture and fsl-mc bus see:
16 same hardware "isolation context" and a 10-bit value called an ICID
21 between ICIDs and IOMMUs, so an iommu-map property is used to define
22 the set of possible ICIDs under a root DPRC and how they map to
28 For arm-smmu binding, see:
31 The MSI writes are accompanied by sideband data which is derived from the ICID.
32 The msi-map property is used to associate the devices with both the ITS
35 For generic MSI bindings, see
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| /kernel/linux/linux-4.19/drivers/of/ |
| D | irq.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8 * Copyright (C) 1996-2001 Cort Dougan
30 * irq_of_parse_and_map - Parse and map an interrupt into linux virq space
32 * @index: Index of the interrupt to map
49 * of_irq_find_parent - Given a device node, find its interrupt parent node
64 if (of_property_read_u32(child, "interrupt-parent", &parent)) { in of_irq_find_parent()
74 } while (p && of_get_property(p, "#interrupt-cells", NULL) == NULL); in of_irq_find_parent()
81 * of_irq_parse_raw - Low level interrupt tree parsing
87 * This function is a low-level interrupt tree walking function. It
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| /kernel/linux/linux-5.10/drivers/of/ |
| D | irq.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8 * Copyright (C) 1996-2001 Cort Dougan
29 * irq_of_parse_and_map - Parse and map an interrupt into linux virq space
31 * @index: Index of the interrupt to map
48 * of_irq_find_parent - Given a device node, find its interrupt parent node
63 if (of_property_read_u32(child, "interrupt-parent", &parent)) { in of_irq_find_parent()
73 } while (p && of_get_property(p, "#interrupt-cells", NULL) == NULL); in of_irq_find_parent()
80 * of_irq_parse_raw - Low level interrupt tree parsing
86 * This function is a low-level interrupt tree walking function. It
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| /kernel/linux/linux-4.19/drivers/pci/controller/ |
| D | pcie-altera-msi.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Altera PCIe MSI support
7 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
13 #include <linux/msi.h>
40 static inline void msi_writel(struct altera_msi *msi, const u32 value, in msi_writel() argument
43 writel_relaxed(value, msi->csr_base + reg); in msi_writel()
46 static inline u32 msi_readl(struct altera_msi *msi, const u32 reg) in msi_readl() argument
48 return readl_relaxed(msi->csr_base + reg); in msi_readl()
54 struct altera_msi *msi; in altera_msi_isr() local
60 msi = irq_desc_get_handler_data(desc); in altera_msi_isr()
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| /kernel/linux/linux-5.10/virt/kvm/ |
| D | irqchip.c | 1 // SPDX-License-Identifier: GPL-2.0-only
29 irq_rt = srcu_dereference_check(kvm->irq_routing, &kvm->irq_srcu, in kvm_irq_map_gsi()
30 lockdep_is_held(&kvm->irq_lock)); in kvm_irq_map_gsi()
31 if (irq_rt && gsi < irq_rt->nr_rt_entries) { in kvm_irq_map_gsi()
32 hlist_for_each_entry(e, &irq_rt->map[gsi], link) { in kvm_irq_map_gsi()
45 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); in kvm_irq_map_chip_pin()
46 return irq_rt->chip[irqchip][pin]; in kvm_irq_map_chip_pin()
49 int kvm_send_userspace_msi(struct kvm *kvm, struct kvm_msi *msi) in kvm_send_userspace_msi() argument
53 if (!irqchip_in_kernel(kvm) || (msi->flags & ~KVM_MSI_VALID_DEVID)) in kvm_send_userspace_msi()
54 return -EINVAL; in kvm_send_userspace_msi()
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| /kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/ |
| D | mpc8641si-post.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
9 #address-cells = <2>;
10 #size-cells = <1>;
11 compatible = "fsl,mpc8641-localbus", "simple-bus";
16 #address-cells = <1>;
17 #size-cells = <1>;
19 compatible = "fsl,mpc8641-soc", "simple-bus";
20 bus-frequency = <0>;
22 mcm-law@0 {
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| /kernel/linux/linux-4.19/arch/powerpc/boot/dts/fsl/ |
| D | mpc8641si-post.dtsi | 4 * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
14 #address-cells = <2>;
15 #size-cells = <1>;
16 compatible = "fsl,mpc8641-localbus", "simple-bus";
21 #address-cells = <1>;
22 #size-cells = <1>;
24 compatible = "fsl,mpc8641-soc", "simple-bus";
25 bus-frequency = <0>;
27 mcm-law@0 {
28 compatible = "fsl,mcm-law";
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| /kernel/linux/linux-4.19/virt/kvm/ |
| D | irqchip.c | 18 * Place - Suite 330, Boston, MA 02111-1307 USA.
41 irq_rt = srcu_dereference_check(kvm->irq_routing, &kvm->irq_srcu, in kvm_irq_map_gsi()
42 lockdep_is_held(&kvm->irq_lock)); in kvm_irq_map_gsi()
43 if (irq_rt && gsi < irq_rt->nr_rt_entries) { in kvm_irq_map_gsi()
44 hlist_for_each_entry(e, &irq_rt->map[gsi], link) { in kvm_irq_map_gsi()
57 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); in kvm_irq_map_chip_pin()
58 return irq_rt->chip[irqchip][pin]; in kvm_irq_map_chip_pin()
61 int kvm_send_userspace_msi(struct kvm *kvm, struct kvm_msi *msi) in kvm_send_userspace_msi() argument
65 if (!irqchip_in_kernel(kvm) || (msi->flags & ~KVM_MSI_VALID_DEVID)) in kvm_send_userspace_msi()
66 return -EINVAL; in kvm_send_userspace_msi()
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| /kernel/linux/linux-5.10/drivers/pci/controller/ |
| D | pcie-altera-msi.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Altera PCIe MSI support
7 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
14 #include <linux/msi.h>
41 static inline void msi_writel(struct altera_msi *msi, const u32 value, in msi_writel() argument
44 writel_relaxed(value, msi->csr_base + reg); in msi_writel()
47 static inline u32 msi_readl(struct altera_msi *msi, const u32 reg) in msi_readl() argument
49 return readl_relaxed(msi->csr_base + reg); in msi_readl()
55 struct altera_msi *msi; in altera_msi_isr() local
61 msi = irq_desc_get_handler_data(desc); in altera_msi_isr()
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| /kernel/linux/linux-5.10/drivers/pci/controller/mobiveil/ |
| D | pcie-mobiveil-host.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright 2019-2020 NXP
19 #include <linux/msi.h>
28 #include "pcie-mobiveil.h"
40 if ((bus->primary == to_pci_host_bridge(bus->bridge)->busnr) && (PCI_SLOT(devfn) > 0)) in mobiveil_pcie_valid_device()
47 * mobiveil_pcie_map_bus - routine to get the configuration base of either
53 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus()
54 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
62 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus()
70 value = bus->number << PAB_BUS_SHIFT | in mobiveil_pcie_map_bus()
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