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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/
Dhisi504-nand.txt1 Hisilicon Hip04 Soc NAND controller DT binding
5 - compatible: Should be "hisilicon,504-nfc".
6 - reg: The first contains base physical address and size of
7 NAND controller's registers. The second contains base
8 physical address and size of NAND controller's buffer.
9 - interrupts: Interrupt number for nfc.
10 - nand-bus-width: See nand-controller.yaml.
11 - nand-ecc-mode: Support none and hw ecc mode.
12 - #address-cells: Partition address, should be set 1.
13 - #size-cells: Partition size, should be set 1.
[all …]
Dmtk-nand.txt1 MTK SoCs NAND FLASH controller (NFC) DT binding
3 This file documents the device tree bindings for MTK SoCs NAND controllers.
5 the nand controller interface driver and the ECC engine driver.
10 1) NFC NAND Controller Interface (NFI):
13 The first part of NFC is NAND Controller Interface (NFI) HW.
15 - compatible: Should be one of
16 "mediatek,mt2701-nfc",
17 "mediatek,mt2712-nfc",
18 "mediatek,mt7622-nfc".
19 - reg: Base physical address and size of NFI.
[all …]
Dnand-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NAND Chip and NAND Controller Generic Binding
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This representation should be
[all …]
Dvf610-nfc.txt1 Freescale's NAND flash controller (NFC)
3 This variant of the Freescale NAND flash controller (NFC) can be found on
7 - compatible: Should be set to "fsl,vf610-nfc".
8 - reg: address range of the NFC.
9 - interrupts: interrupt of the NFC.
10 - #address-cells: shall be set to 1. Encode the nand CS.
11 - #size-cells : shall be set to 0.
12 - assigned-clocks: main clock from the SoC, for Vybrid <&clks VF610_CLK_NFC>;
13 - assigned-clock-rates: The NAND bus timing is derived from this clock
14 rate and should not exceed maximum timing for any NAND memory chip
[all …]
Dmarvell-nand.txt1 Marvell NAND Flash Controller (NFC)
4 - compatible: can be one of the following:
5 * "marvell,armada-8k-nand-controller"
6 * "marvell,armada370-nand-controller"
7 * "marvell,pxa3xx-nand-controller"
8 * "marvell,armada-8k-nand" (deprecated)
9 * "marvell,armada370-nand" (deprecated)
10 * "marvell,pxa3xx-nand" (deprecated)
13 - reg: NAND flash controller memory area.
14 - #address-cells: shall be set to 1. Encode the NAND CS.
[all …]
Ddenali,nand.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mtd/denali,nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Denali NAND controller
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
15 - altr,socfpga-denali-nand
16 - socionext,uniphier-denali-nand-v5a
17 - socionext,uniphier-denali-nand-v5b
19 reg-names:
[all …]
Dbrcm,brcmnand.txt1 * Broadcom STB NAND Controller
3 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
4 flash chips. It has a memory-mapped register interface for both control
15 - compatible : May contain an SoC-specific compatibility string (see below)
16 to account for any SoC-specific hardware bits that may be
19 the core NAND controller, of the following form:
21 string, like "brcm,brcmnand-v7.0"
23 brcm,brcmnand-v2.1
24 brcm,brcmnand-v2.2
25 brcm,brcmnand-v4.0
[all …]
Dtango-nand.txt1 Sigma Designs Tango4 NAND Flash Controller (NFC)
5 - compatible: "sigma,smp8758-nand"
6 - reg: address/size of nfc_reg, nfc_mem, and pbus_reg
7 - dmas: reference to the DMA channel used by the controller
8 - dma-names: "rxtx"
9 - clocks: reference to the system clock
10 - #address-cells: <1>
11 - #size-cells: <0>
13 Children nodes represent the available NAND chips.
14 See Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindings.
[all …]
Dnvidia-tegra20-nand.txt1 NVIDIA Tegra NAND Flash controller
4 - compatible: Must be one of:
5 - "nvidia,tegra20-nand"
6 - reg: MMIO address range
7 - interrupts: interrupt output of the NFC controller
8 - clocks: Must contain an entry for each entry in clock-names.
9 See ../clocks/clock-bindings.txt for details.
10 - clock-names: Must include the following entries:
11 - nand
12 - resets: Must contain an entry for each entry in reset-names.
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/mtd/
Dhisi504-nand.txt1 Hisilicon Hip04 Soc NAND controller DT binding
5 - compatible: Should be "hisilicon,504-nfc".
6 - reg: The first contains base physical address and size of
7 NAND controller's registers. The second contains base
8 physical address and size of NAND controller's buffer.
9 - interrupts: Interrupt number for nfc.
10 - nand-bus-width: See nand.txt.
11 - nand-ecc-mode: Support none and hw ecc mode.
12 - #address-cells: Partition address, should be set 1.
13 - #size-cells: Partition size, should be set 1.
[all …]
Dmtk-nand.txt1 MTK SoCs NAND FLASH controller (NFC) DT binding
3 This file documents the device tree bindings for MTK SoCs NAND controllers.
5 the nand controller interface driver and the ECC engine driver.
10 1) NFC NAND Controller Interface (NFI):
13 The first part of NFC is NAND Controller Interface (NFI) HW.
15 - compatible: Should be one of
16 "mediatek,mt2701-nfc",
17 "mediatek,mt2712-nfc",
18 "mediatek,mt7622-nfc".
19 - reg: Base physical address and size of NFI.
[all …]
Dnand.txt1 * NAND chip and NAND controller generic binding
3 NAND controller/NAND chip representation:
5 The NAND controller should be represented with its own DT node, and all
6 NAND chips attached to this controller should be defined as children nodes
7 of the NAND controller. This representation should be enforced even for
10 Mandatory NAND controller properties:
11 - #address-cells: depends on your controller. Should at least be 1 to
13 - #size-cells: depends on your controller. Put zero unless you need a
16 Optional NAND controller properties
17 - ranges: only needed if you need to define a mapping between CS lines and
[all …]
Dvf610-nfc.txt1 Freescale's NAND flash controller (NFC)
3 This variant of the Freescale NAND flash controller (NFC) can be found on
7 - compatible: Should be set to "fsl,vf610-nfc".
8 - reg: address range of the NFC.
9 - interrupts: interrupt of the NFC.
10 - #address-cells: shall be set to 1. Encode the nand CS.
11 - #size-cells : shall be set to 0.
12 - assigned-clocks: main clock from the SoC, for Vybrid <&clks VF610_CLK_NFC>;
13 - assigned-clock-rates: The NAND bus timing is derived from this clock
14 rate and should not exceed maximum timing for any NAND memory chip
[all …]
Dmarvell-nand.txt1 Marvell NAND Flash Controller (NFC)
4 - compatible: can be one of the following:
5 * "marvell,armada-8k-nand-controller"
6 * "marvell,armada370-nand-controller"
7 * "marvell,pxa3xx-nand-controller"
8 * "marvell,armada-8k-nand" (deprecated)
9 * "marvell,armada370-nand" (deprecated)
10 * "marvell,pxa3xx-nand" (deprecated)
13 - reg: NAND flash controller memory area.
14 - #address-cells: shall be set to 1. Encode the NAND CS.
[all …]
Dbrcm,brcmnand.txt1 * Broadcom STB NAND Controller
3 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
4 flash chips. It has a memory-mapped register interface for both control
15 - compatible : May contain an SoC-specific compatibility string (see below)
16 to account for any SoC-specific hardware bits that may be
19 the core NAND controller, of the following form:
21 string, like "brcm,brcmnand-v7.0"
23 brcm,brcmnand-v4.0
24 brcm,brcmnand-v5.0
25 brcm,brcmnand-v6.0
[all …]
Dingenic,jz4780-nand.txt1 * Ingenic JZ4780 NAND/BCH
3 This file documents the device tree bindings for NAND flash devices on the
4 JZ4780. NAND devices are connected to the NEMC controller (described in
5 memory-controllers/ingenic,jz4780-nemc.txt), and thus NAND device nodes must
8 Required NAND controller device properties:
9 - compatible: Should be set to "ingenic,jz4780-nand".
10 - reg: For each bank with a NAND chip attached, should specify a bank number,
11 an offset of 0 and a size of 0x1000000 (i.e. the whole NEMC bank).
13 Optional NAND controller device properties:
14 - ingenic,bch-controller: To make use of the hardware BCH controller, this
[all …]
Dgpmi-nand.txt1 * Freescale General-Purpose Media Interface (GPMI)
3 The GPMI nand controller provides an interface to control the
4 NAND flash chips.
7 - compatible : should be "fsl,<chip>-gpmi-nand", chip can be:
13 - reg : should contain registers location and length for gpmi and bch.
14 - reg-names: Should contain the reg names "gpmi-nand" and "bch"
15 - interrupts : BCH interrupt number.
16 - interrupt-names : Should be "bch".
17 - dmas: DMA specifier, consisting of a phandle to DMA controller node
19 Refer to dma.txt and fsl-mxs-dma.txt for details.
[all …]
Dtango-nand.txt1 Sigma Designs Tango4 NAND Flash Controller (NFC)
5 - compatible: "sigma,smp8758-nand"
6 - reg: address/size of nfc_reg, nfc_mem, and pbus_reg
7 - dmas: reference to the DMA channel used by the controller
8 - dma-names: "rxtx"
9 - clocks: reference to the system clock
10 - #address-cells: <1>
11 - #size-cells: <0>
13 Children nodes represent the available NAND chips.
14 See Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
[all …]
Ddenali-nand.txt1 * Denali NAND controller
4 - compatible : should be one of the following:
5 "altr,socfpga-denali-nand" - for Altera SOCFPGA
6 "socionext,uniphier-denali-nand-v5a" - for Socionext UniPhier (v5a)
7 "socionext,uniphier-denali-nand-v5b" - for Socionext UniPhier (v5b)
8 - reg : should contain registers location and length for data and reg.
9 - reg-names: Should contain the reg names "nand_data" and "denali_reg"
10 - interrupts : The interrupt number.
11 - clocks: should contain phandle of the controller core clock, the bus
12 interface clock, and the ECC circuit clock.
[all …]
/kernel/linux/linux-5.10/include/linux/mtd/
Drawnand.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
8 * Contains standard defines and IDs for NAND flash devices
17 #include <linux/mtd/nand.h>
21 #include <linux/mtd/nand.h>
29 /* The maximum number of NAND chips in an array */
50 * Standard NAND flash commands
73 #define NAND_CMD_NONE -1
82 #define NAND_DATA_IFACE_CHECK_ONLY -1
85 * Constants for Hardware ECC
[all …]
/kernel/linux/linux-4.19/include/linux/mtd/
Drawnand.h2 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
11 * Contains standard defines and IDs for NAND flash devices
30 /* Scan and identify a NAND device */
42 /* The maximum number of NAND chips in an array */
63 * Standard NAND flash commands
86 #define NAND_CMD_NONE -1
95 #define NAND_DATA_IFACE_CHECK_ONLY -1
117 * Constants for Hardware ECC
119 /* Reset Hardware ECC for read */
121 /* Reset Hardware ECC for write */
[all …]
/kernel/linux/linux-5.10/drivers/mtd/nand/raw/
Dsunxi_nand.c1 // SPDX-License-Identifier: GPL-2.0+
6 * https://github.com/yuq/sunxi-nfc-mtd
9 * https://github.com/hno/Allwinner-Info
16 #include <linux/dma-mapping.h>
70 #define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8)
107 #define NFC_ADR_NUM(x) (((x) - 1) << 16)
161 * struct sunxi_nand_chip_sel - stores information related to NAND Chip Select
163 * @cs: the NAND CS id used to communicate with a NAND Chip
164 * @rb: the Ready/Busy pin ID. -1 means no R/B pin connected to the NFC
172 * struct sunxi_nand_hw_ecc - stores information related to HW ECC support
[all …]
/kernel/linux/linux-5.10/Documentation/ABI/testing/
Dsysfs-class-mtd4 Contact: linux-mtd@lists.infradead.org
12 Contact: linux-mtd@lists.infradead.org
22 Contact: linux-mtd@lists.infradead.org
24 These directories provide the corresponding read-only device
30 Contact: linux-mtd@lists.infradead.org
34 read-write device so <minor> will be even.
39 Contact: linux-mtd@lists.infradead.org
42 to the read-only variant of thie MTD device (in
48 Contact: linux-mtd@lists.infradead.org
50 "Major" erase size for the device. If numeraseregions is
[all …]
/kernel/linux/linux-4.19/Documentation/ABI/testing/
Dsysfs-class-mtd4 Contact: linux-mtd@lists.infradead.org
12 Contact: linux-mtd@lists.infradead.org
22 Contact: linux-mtd@lists.infradead.org
24 These directories provide the corresponding read-only device
30 Contact: linux-mtd@lists.infradead.org
34 read-write device so <minor> will be even.
39 Contact: linux-mtd@lists.infradead.org
42 to the read-only variant of thie MTD device (in
48 Contact: linux-mtd@lists.infradead.org
50 "Major" erase size for the device. If numeraseregions is
[all …]
/kernel/linux/linux-4.19/drivers/mtd/nand/raw/
Dsunxi_nand.c5 * https://github.com/yuq/sunxi-nfc-mtd
8 * https://github.com/hno/Allwinner-Info
25 #include <linux/dma-mapping.h>
77 #define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8)
113 #define NFC_ADR_NUM(x) (((x) - 1) << 16)
167 * Chip Select structure: stores information related to NAND Chip Select
169 * @cs: the NAND CS id used to communicate with a NAND Chip
170 * @rb: the Ready/Busy pin ID. -1 means no R/B pin connected to the
179 * sunxi HW ECC infos: stores information related to HW ECC support
181 * @mode: the sunxi ECC mode field deduced from ECC requirements
[all …]

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