| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/ |
| D | nand-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NAND Chip and NAND Controller Generic Binding
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This representation should be
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| /kernel/linux/linux-5.10/drivers/mtd/nand/ |
| D | ecc.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Generic Error-Correcting Code (ECC) engine
10 * This file describes the abstraction of any NAND ECC engine. It has been
11 * designed to fit most cases, including parallel NANDs and SPI-NANDs.
13 * There are three main situations where instantiating this ECC engine makes
15 * - external: The ECC engine is outside the NAND pipeline, typically this
16 * is a software ECC engine, or an hardware engine that is
17 * outside the NAND controller pipeline.
18 * - pipelined: The ECC engine is inside the NAND pipeline, ie. on the
19 * controller's side. This is the case of most of the raw NAND
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| /kernel/linux/linux-5.10/include/linux/mtd/ |
| D | nand.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2017 - Free Electrons
6 * Boris Brezillon <boris.brezillon@free-electrons.com>
18 * struct nand_memory_organization - Memory organization structure
19 * @bits_per_cell: number of bits per NAND cell
27 * @ntargets: total number of targets exposed by the NAND device
55 * struct nand_row_converter - Information needed to convert an absolute offset
67 * struct nand_pos - NAND position object
68 * @target: the NAND target/die
74 * These information are usually used by specific sub-layers to select the
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| D | rawnand.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
8 * Contains standard defines and IDs for NAND flash devices
17 #include <linux/mtd/nand.h>
21 #include <linux/mtd/nand.h>
29 /* The maximum number of NAND chips in an array */
50 * Standard NAND flash commands
73 #define NAND_CMD_NONE -1
82 #define NAND_DATA_IFACE_CHECK_ONLY -1
85 * Constants for Hardware ECC
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| /kernel/linux/linux-5.10/drivers/mtd/nand/raw/ |
| D | omap2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
20 #include <linux/omap-dma.h>
29 #include <linux/omap-gpmc.h>
30 #include <linux/platform_data/mtd-nand-omap2.h>
32 #define DRIVER_NAME "omap2-nand"
122 /* GPMC ecc engine settings for read */
129 /* GPMC ecc engine settings for write */
131 #define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */
145 struct nand_chip nand; member
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "NAND ECC Smart Media byte order"
10 Software ECC according to the Smart Media Specification.
14 tristate "Raw/Parallel NAND Device Support"
20 NAND flash devices. For further information see
21 <http://www.linux-mtd.infradead.org/doc/nand.html>.
26 bool "Support software BCH ECC"
32 ECC codes. They are used with NAND devices requiring more than 1 bit
35 comment "Raw/parallel NAND flash controllers"
41 tristate "Denali NAND controller on Intel Moorestown"
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| D | marvell_nand.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell NAND flash controller driver
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
9 * This NAND controller driver handles two versions of the hardware,
13 * The main visible difference is that NFCv1 only has Hamming ECC
14 * capabilities, while NFCv2 also embeds a BCH ECC engine. Also, DMA
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
21 * or 4) and each chunk will have its own ECC "digest" of 6B at the
23 * bytes (also called "spare" bytes in the driver). This engine
28 * +-------------------------------------------------------------+
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| D | arasan-nand-controller.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Arasan NAND Flash Controller Driver
5 * Copyright (C) 2014 - 2020 Xilinx, Inc.
17 #include <linux/dma-mapping.h>
103 #define ANFC_MAX_PKT_SIZE (SZ_2K - 1)
111 * struct anfc_op - Defines how to execute an operation
136 * struct anand - Defines the NAND chip related information
137 * @node: Used to store NAND chips into a list
138 * @chip: NAND chip information structure
140 * @rb: Ready-busy line
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| D | nand_base.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * This is the generic MTD driver for NAND flash devices. It should be
5 * capable of working with almost all NAND chips currently available.
8 * http://www.linux-mtd.infradead.org/doc/nand.html
11 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
21 * Check, if mtd->ecctype should be set to MTD_ECC_HW
22 * if we have HW ECC support.
37 #include <linux/mtd/nand.h>
52 int lastpage = (mtd->erasesize / mtd->writesize) - 1; in nand_pairing_dist3_get_info()
59 info->group = 0; in nand_pairing_dist3_get_info()
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| D | r852.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2009 - Maxim Levitsky
14 /* nand interface + ecc
15 byte write/read does one cycle on nand data lines.
18 results of ecc correction, if DMA read was done before.
19 If write was done two dword reads read generated ecc checksums
30 #define R852_CTL_CARDENABLE 0x10 /* probably (#CE) - always set*/
31 #define R852_CTL_ECC_ENABLE 0x20 /* enable ecc engine */
32 #define R852_CTL_ECC_ACCESS 0x40 /* read/write ecc via reg #0*/
42 #define R852_CARD_STA_BUSY 0x80 /* card is busy - (#R/B) */
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| D | cadence-nand-controller.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Cadence NAND flash controller driver
12 #include <linux/dma-mapping.h>
24 * - PIO - can work in master or slave DMA
25 * - CDMA - needs Master DMA for accessing command descriptors.
26 * - Generic mode - can use only slave DMA.
29 * on NAND flash memory. Driver uses CDMA mode for
88 /* Command Engine threads state. */
91 /* Command Engine interrupt thread error status. */
93 /* Command Engine interrupt thread error enable. */
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| D | stm32_fmc2_nand.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/dma-mapping.h>
26 /* ECC step size */
35 /* Max requests done for a 8k nand page size */
41 /* Max ECC buffer length */
246 struct stm32_fmc2_nand nand; member
281 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); in stm32_fmc2_nfc_timings_init()
282 struct stm32_fmc2_nand *nand = to_fmc2_nand(chip); in stm32_fmc2_nfc_timings_init() local
283 struct stm32_fmc2_timings *timings = &nand->timings; in stm32_fmc2_nfc_timings_init()
287 regmap_update_bits(nfc->regmap, FMC2_PCR, in stm32_fmc2_nfc_timings_init()
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| D | davinci_nand.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * davinci_nand.c - NAND Flash Driver for DaVinci family chips
8 * Sander Huijsen <Shuijsen@optelecom-nkf.com>
24 #include <linux/platform_data/mtd-davinci.h>
25 #include <linux/platform_data/mtd-davinci-aemif.h>
28 * This is a device driver for the NAND flash controller found on the
33 * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC
34 * available on chips like the DM355 and OMAP-L137 and needed with the
35 * more error-prone MLC NAND chips.
37 * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
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| /kernel/linux/linux-4.19/drivers/mtd/nand/raw/ |
| D | omap2.c | 13 #include <linux/dma-mapping.h>
23 #include <linux/omap-dma.h>
32 #include <linux/omap-gpmc.h>
33 #include <linux/platform_data/mtd-nand-omap2.h>
35 #define DRIVER_NAME "omap2-nand"
125 /* GPMC ecc engine settings for read */
132 /* GPMC ecc engine settings for write */
134 #define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */
148 struct nand_chip nand; member
173 /* fields specific for BCHx_HW ECC scheme */
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| D | Kconfig | 5 bool "NAND ECC Smart Media byte order"
9 Software ECC according to the Smart Media Specification.
14 tristate "Raw/Parallel NAND Device Support"
19 NAND flash devices. For further information see
20 <http://www.linux-mtd.infradead.org/doc/nand.html>.
31 bool "Support software BCH ECC"
36 ECC codes. They are used with NAND devices requiring more than 1 bit
47 tristate "Support Denali NAND controller on Intel Moorestown"
51 Enable the driver for NAND flash on Intel Moorestown, using the
52 Denali NAND controller core.
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| D | nand_base.c | 3 * This is the generic MTD driver for NAND flash devices. It should be
4 * capable of working with almost all NAND chips currently available.
7 * http://www.linux-mtd.infradead.org/doc/nand.html
10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
20 * Check, if mtd->ecctype should be set to MTD_ECC_HW
21 * if we have HW ECC support.
61 struct nand_ecc_ctrl *ecc = &chip->ecc; in nand_ooblayout_ecc_sp() local
64 return -ERANGE; in nand_ooblayout_ecc_sp()
67 oobregion->offset = 0; in nand_ooblayout_ecc_sp()
68 if (mtd->oobsize == 16) in nand_ooblayout_ecc_sp()
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| D | marvell_nand.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell NAND flash controller driver
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
22 #include <linux/dma-mapping.h>
23 #include <linux/dma/pxa-dma.h>
24 #include <linux/platform_data/mtd-nand-pxa3xx.h>
44 /* System control registers/bits to enable the NAND controller on some SoCs */
55 /* NAND controller data flash control register */
74 /* NAND interface timing parameter 0 register */
88 /* NAND interface timing parameter 1 register */
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| D | r852.h | 2 * Copyright © 2009 - Maxim Levitsky
17 /* nand interface + ecc
18 byte write/read does one cycle on nand data lines.
21 results of ecc correction, if DMA read was done before.
22 If write was done two dword reads read generated ecc checksums
33 #define R852_CTL_CARDENABLE 0x10 /* probably (#CE) - always set*/
34 #define R852_CTL_ECC_ENABLE 0x20 /* enable ecc engine */
35 #define R852_CTL_ECC_ACCESS 0x40 /* read/write ecc via reg #0*/
45 #define R852_CARD_STA_BUSY 0x80 /* card is busy - (#R/B) */
74 /* physical DMA address - 32 bit value*/
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| D | davinci_nand.c | 2 * davinci_nand.c - NAND Flash Driver for DaVinci family chips
7 * Sander Huijsen <Shuijsen@optelecom-nkf.com>
37 #include <linux/platform_data/mtd-davinci.h>
38 #include <linux/platform_data/mtd-davinci-aemif.h>
41 * This is a device driver for the NAND flash controller found on the
46 * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC
47 * available on chips like the DM355 and OMAP-L137 and needed with the
48 * more error-prone MLC NAND chips.
50 * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
51 * outputs in a "wire-AND" configuration, with no per-chip signals.
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| /kernel/linux/linux-5.10/drivers/mtd/nand/raw/ingenic/ |
| D | ingenic_ecc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * JZ47xx ECC common code
18 * ingenic_ecc_calculate() - calculate ECC for a data buffer
19 * @ecc: ECC device.
20 * @params: ECC parameters.
22 * @ecc_code: output buffer with ECC.
24 * Return: 0 on success, -ETIMEDOUT if timed out while waiting for ECC
27 int ingenic_ecc_calculate(struct ingenic_ecc *ecc, in ingenic_ecc_calculate() argument
31 return ecc->ops->calculate(ecc, params, buf, ecc_code); in ingenic_ecc_calculate()
35 * ingenic_ecc_correct() - detect and correct bit errors
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| D | ingenic_nand_drv.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Ingenic JZ47xx NAND driver
24 #include <linux/jz4780-nemc.h>
28 #define DRV_NAME "ingenic-nand"
44 struct ingenic_ecc *ecc; member
75 struct nand_ecc_ctrl *ecc = &chip->ecc; in qi_lb60_ooblayout_ecc() local
77 if (section || !ecc->total) in qi_lb60_ooblayout_ecc()
78 return -ERANGE; in qi_lb60_ooblayout_ecc()
80 oobregion->length = ecc->total; in qi_lb60_ooblayout_ecc()
81 oobregion->offset = 12; in qi_lb60_ooblayout_ecc()
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| /kernel/linux/linux-4.19/drivers/mtd/nand/raw/gpmi-nand/ |
| D | gpmi-nand.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale GPMI NAND Flash Driver
5 * Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
16 #include "gpmi-nand.h"
17 #include "bch-regs.h"
19 /* Resource names for the GPMI NAND driver. */
20 #define GPMI_NAND_GPMI_REGS_ADDR_RES_NAME "gpmi-nand"
34 * We may change the layout if we can get the ECC info from the datasheet,
42 struct bch_geometry *geo = &this->bch_geometry; in gpmi_ooblayout_ecc()
45 return -ERANGE; in gpmi_ooblayout_ecc()
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| /kernel/linux/linux-4.19/include/linux/mtd/ |
| D | rawnand.h | 2 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
11 * Contains standard defines and IDs for NAND flash devices
30 /* Scan and identify a NAND device */
42 /* The maximum number of NAND chips in an array */
63 * Standard NAND flash commands
86 #define NAND_CMD_NONE -1
95 #define NAND_DATA_IFACE_CHECK_ONLY -1
117 * Constants for Hardware ECC
119 /* Reset Hardware ECC for read */
121 /* Reset Hardware ECC for write */
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| /kernel/linux/linux-5.10/drivers/mtd/nand/raw/gpmi-nand/ |
| D | gpmi-nand.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale GPMI NAND Flash Driver
5 * Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
18 #include <linux/dma/mxs-dma.h>
19 #include "gpmi-nand.h"
20 #include "gpmi-regs.h"
21 #include "bch-regs.h"
23 /* Resource names for the GPMI NAND driver. */
24 #define GPMI_NAND_GPMI_REGS_ADDR_RES_NAME "gpmi-nand"
52 while ((readl(addr) & mask) && --timeout) in clear_poll_bit()
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| /kernel/linux/linux-5.10/drivers/mtd/nand/raw/atmel/ |
| D | pmecc.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
13 * Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
19 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
22 * Derived from Das U-Boot source code
23 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
26 * Add Programmable Multibit ECC support for various AT91 SoC
29 * Add Nand Flash Controller support for SAMA5 SoC
32 * The PMECC is an hardware assisted BCH engine, which means part of the
33 * ECC algorithm is left to the software. The hardware/software repartition
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