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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/mtd/
Dsunxi-nand.txt1 Allwinner NAND Flash Controller (NFC)
4 - compatible : "allwinner,sun4i-a10-nand".
5 - reg : shall contain registers location and length for data and reg.
6 - interrupts : shall define the nand controller interrupt.
7 - #address-cells: shall be set to 1. Encode the nand CS.
8 - #size-cells : shall be set to 0.
9 - clocks : shall reference nand controller clocks.
10 - clock-names : nand controller internal clock names. Shall contain :
12 * "mod" : nand controller clock
15 - dmas : shall reference DMA channel associated to the NAND controller.
[all …]
Dingenic,jz4780-nand.txt1 * Ingenic JZ4780 NAND/BCH
3 This file documents the device tree bindings for NAND flash devices on the
4 JZ4780. NAND devices are connected to the NEMC controller (described in
5 memory-controllers/ingenic,jz4780-nemc.txt), and thus NAND device nodes must
8 Required NAND controller device properties:
9 - compatible: Should be set to "ingenic,jz4780-nand".
10 - reg: For each bank with a NAND chip attached, should specify a bank number,
13 Optional NAND controller device properties:
14 - ingenic,bch-controller: To make use of the hardware BCH controller, this
20 - Individual NAND chips are children of the NAND controller node.
[all …]
Dmarvell-nand.txt1 Marvell NAND Flash Controller (NFC)
4 - compatible: can be one of the following:
5 * "marvell,armada-8k-nand-controller"
6 * "marvell,armada370-nand-controller"
7 * "marvell,pxa3xx-nand-controller"
8 * "marvell,armada-8k-nand" (deprecated)
9 * "marvell,armada370-nand" (deprecated)
10 * "marvell,pxa3xx-nand" (deprecated)
13 - reg: NAND flash controller memory area.
14 - #address-cells: shall be set to 1. Encode the NAND CS.
[all …]
Datmel-nand.txt1 Atmel NAND flash controller bindings
3 The NAND flash controller node should be defined under the EBI bus (see
4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
5 One or several NAND devices can be defined under this NAND controller.
6 The NAND controller might be connected to an ECC engine.
8 * NAND controller bindings:
11 - compatible: should be one of the following
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
[all …]
Dgpmc-nand.txt3 GPMC connected NAND (found on OMAP boards) are represented as child nodes of
4 the GPMC controller with a name of "nand".
7 explained in a separate documents - please refer to
8 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
10 For NAND specific properties such as ECC modes or bus width, please refer to
11 Documentation/devicetree/bindings/mtd/nand.txt
16 - compatible: "ti,omap2-nand"
17 - reg: range id (CS number), base offset and length of the
18 NAND I/O space
19 - interrupts: Two interrupt specifiers, one for fifoevent, one for termcount.
[all …]
Dnand.txt1 * NAND chip and NAND controller generic binding
3 NAND controller/NAND chip representation:
5 The NAND controller should be represented with its own DT node, and all
6 NAND chips attached to this controller should be defined as children nodes
7 of the NAND controller. This representation should be enforced even for
10 Mandatory NAND controller properties:
11 - #address-cells: depends on your controller. Should at least be 1 to
13 - #size-cells: depends on your controller. Put zero unless you need a
16 Optional NAND controller properties
17 - ranges: only needed if you need to define a mapping between CS lines and
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/
Datmel-nand.txt1 Atmel NAND flash controller bindings
3 The NAND flash controller node should be defined under the EBI bus (see
4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
5 One or several NAND devices can be defined under this NAND controller.
6 The NAND controller might be connected to an ECC engine.
8 * NAND controller bindings:
11 - compatible: should be one of the following
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
[all …]
Dmarvell-nand.txt1 Marvell NAND Flash Controller (NFC)
4 - compatible: can be one of the following:
5 * "marvell,armada-8k-nand-controller"
6 * "marvell,armada370-nand-controller"
7 * "marvell,pxa3xx-nand-controller"
8 * "marvell,armada-8k-nand" (deprecated)
9 * "marvell,armada370-nand" (deprecated)
10 * "marvell,pxa3xx-nand" (deprecated)
13 - reg: NAND flash controller memory area.
14 - #address-cells: shall be set to 1. Encode the NAND CS.
[all …]
Dnand-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NAND Chip and NAND Controller Generic Binding
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This representation should be
[all …]
Dgpmc-nand.txt3 GPMC connected NAND (found on OMAP boards) are represented as child nodes of
4 the GPMC controller with a name of "nand".
7 explained in a separate documents - please refer to
8 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
10 For NAND specific properties such as ECC modes or bus width, please refer to
11 Documentation/devicetree/bindings/mtd/nand-controller.yaml
16 - compatible: "ti,omap2-nand"
17 - reg: range id (CS number), base offset and length of the
18 NAND I/O space
19 - interrupts: Two interrupt specifiers, one for fifoevent, one for termcount.
[all …]
Dallwinner,sun4i-a10-nand.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/allwinner,sun4i-a10-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 NAND Controller Device Tree Bindings
10 - $ref: "nand-controller.yaml"
13 - Chen-Yu Tsai <wens@csie.org>
14 - Maxime Ripard <mripard@kernel.org>
17 "#address-cells": true
18 "#size-cells": true
[all …]
/kernel/linux/linux-4.19/drivers/mtd/nand/raw/atmel/
Dnand-controller.c5 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
12 * Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
22 * Derived from Das U-Boot source code
23 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
29 * Add Nand Flash Controller support for SAMA5 SoC
41 * - atmel_nand_: all generic structures/functions
42 * - atmel_smc_nand_: all structures/functions specific to the SMC interface
44 * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
46 * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
48 * - <soc>_nand_: all SoC specific structures/functions
[all …]
/kernel/linux/linux-5.10/drivers/mtd/nand/raw/atmel/
Dnand-controller.c1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
13 * Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
23 * Derived from Das U-Boot source code
24 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
30 * Add Nand Flash Controller support for SAMA5 SoC
38 * - atmel_nand_: all generic structures/functions
39 * - atmel_smc_nand_: all structures/functions specific to the SMC interface
41 * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
43 * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dpm9g45.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * pm9g45.dts - Device Tree file for Ronetix pm9g45 board
5 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 /dts-v1/;
24 clock-frequency = <32768>;
28 clock-frequency = <12000000>;
39 nand {
40 pinctrl_nand_rb: nand-rb-0 {
47 pinctrl_board_mmc: mmc0-board {
56 compatible = "atmel,tcb-timer";
[all …]
Dat91-linea.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91-linea.dtsi - Device Tree Include file for the Axentia Linea Module.
22 clock-frequency = <32768>;
26 clock-frequency = <12000000>;
31 compatible = "atmel,tcb-timer";
36 compatible = "atmel,tcb-timer";
52 pinctrl-0 = <&pinctrl_ebi_nand_addr>;
53 pinctrl-names = "default";
61 nand: nand@3 { label
63 atmel,rb = <0>;
[all …]
Dge863-pro3.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ge863_pro3.dtsi - Device Tree file for Telit GE863-PRO3
14 clock-frequency = <6000000>;
22 compatible = "atmel,tcb-timer";
27 compatible = "atmel,tcb-timer";
40 nand_controller: nand-controller {
42 pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
43 pinctrl-names = "default";
45 nand@3 {
47 rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
[all …]
Dsun8i-r16-nintendo-nes-classic.dts1 // SPDX-License-Identifier: GPL-2.0 OR X11
4 /dts-v1/;
5 #include "sun8i-a33.dtsi"
6 #include "sunxi-common-regulators.dtsi"
10 compatible = "nintendo,nes-classic", "allwinner,sun8i-r16",
11 "allwinner,sun8i-a33";
18 stdout-path = "serial0:115200n8";
27 pinctrl-names = "default";
28 pinctrl-0 = <&uart0_pf_pins>;
36 nand@0 {
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dpm9g45.dts2 * pm9g45.dts - Device Tree file for Ronetix pm9g45 board
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8 /dts-v1/;
25 clock-frequency = <32768>;
29 clock-frequency = <12000000>;
40 nand {
41 pinctrl_nand_rb: nand-rb-0 {
48 pinctrl_board_mmc: mmc0-board {
57 compatible = "atmel,tcb-timer";
62 compatible = "atmel,tcb-timer";
[all …]
Dat91-linea.dtsi2 * at91-linea.dtsi - Device Tree Include file for the Axentia Linea Module.
23 clock-frequency = <32768>;
27 clock-frequency = <12000000>;
32 compatible = "atmel,tcb-timer";
37 compatible = "atmel,tcb-timer";
53 pinctrl-0 = <&pinctrl_ebi_nand_addr>;
54 pinctrl-names = "default";
62 nand: nand@3 { label
64 atmel,rb = <0>;
65 nand-bus-width = <8>;
[all …]
Dge863-pro3.dtsi2 * ge863_pro3.dtsi - Device Tree file for Telit GE863-PRO3
15 clock-frequency = <6000000>;
23 compatible = "atmel,tcb-timer";
28 compatible = "atmel,tcb-timer";
41 nand_controller: nand-controller {
43 pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
44 pinctrl-names = "default";
46 nand@3 {
48 rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
49 cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
[all …]
Dsun8i-r16-nintendo-nes-classic.dts1 // SPDX-License-Identifier: GPL-2.0 OR X11
4 /dts-v1/;
5 #include "sun8i-a33.dtsi"
6 #include "sunxi-common-regulators.dtsi"
10 compatible = "nintendo,nes-classic", "allwinner,sun8i-r16",
11 "allwinner,sun8i-a33";
18 stdout-path = "serial0:115200n8";
27 pinctrl-names = "default";
28 pinctrl-0 = <&uart0_pins_a>;
36 nand@0 {
[all …]
/kernel/linux/linux-4.19/drivers/mtd/nand/raw/
Dmarvell_nand.c1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell NAND flash controller driver
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
22 #include <linux/dma-mapping.h>
23 #include <linux/dma/pxa-dma.h>
24 #include <linux/platform_data/mtd-nand-pxa3xx.h>
44 /* System control registers/bits to enable the NAND controller on some SoCs */
55 /* NAND controller data flash control register */
74 /* NAND interface timing parameter 0 register */
88 /* NAND interface timing parameter 1 register */
[all …]
Dsunxi_nand.c5 * https://github.com/yuq/sunxi-nfc-mtd
8 * https://github.com/hno/Allwinner-Info
25 #include <linux/dma-mapping.h>
77 #define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8)
113 #define NFC_ADR_NUM(x) (((x) - 1) << 16)
167 * Chip Select structure: stores information related to NAND Chip Select
169 * @cs: the NAND CS id used to communicate with a NAND Chip
170 * @rb: the Ready/Busy pin ID. -1 means no R/B pin connected to the
175 s8 rb; member
188 * NAND chip structure: stores NAND chip device related information
[all …]
/kernel/linux/linux-5.10/drivers/mtd/nand/raw/
Dmarvell_nand.c1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell NAND flash controller driver
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
9 * This NAND controller driver handles two versions of the hardware,
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
28 * +-------------------------------------------------------------+
30 * +-------------------------------------------------------------+
39 * +-----------------------------------------
41 * +-----------------------------------------
43 * -------------------------------------------
[all …]
Darasan-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0
3 * Arasan NAND Flash Controller Driver
5 * Copyright (C) 2014 - 2020 Xilinx, Inc.
17 #include <linux/dma-mapping.h>
103 #define ANFC_MAX_PKT_SIZE (SZ_2K - 1)
111 * struct anfc_op - Defines how to execute an operation
136 * struct anand - Defines the NAND chip related information
137 * @node: Used to store NAND chips into a list
138 * @chip: NAND chip information structure
140 * @rb: Ready-busy line
[all …]

123456789