| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/ |
| D | secure.txt | 1 * ARM Secure world bindings
4 "Normal" and "Secure". Most devicetree consumers (including the Linux
6 world or the Secure world. However some devicetree consumers are
8 visible only in the Secure address space, only in the Normal address
10 virtual machine which boots Secure firmware and wants to tell the
13 The general principle of the naming scheme for Secure world bindings
14 is that any property that needs a different value in the Secure world
15 can be supported by prefixing the property name with "secure-". So for
16 instance "secure-foo" would override "foo". For property names with
17 a vendor prefix, the Secure variant of "vendor,foo" would be
[all …]
|
| D | pmu.txt | 5 representation in the device tree should be done as under:-
9 - compatible : should be one of
10 "apm,potenza-pmu"
11 "arm,armv8-pmuv3"
12 "arm,cortex-a73-pmu"
13 "arm,cortex-a72-pmu"
14 "arm,cortex-a57-pmu"
15 "arm,cortex-a53-pmu"
16 "arm,cortex-a35-pmu"
17 "arm,cortex-a17-pmu"
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | secure.txt | 1 * ARM Secure world bindings
4 "Normal" and "Secure". Most devicetree consumers (including the Linux
6 world or the Secure world. However some devicetree consumers are
8 visible only in the Secure address space, only in the Normal address
10 virtual machine which boots Secure firmware and wants to tell the
13 The general principle of the naming scheme for Secure world bindings
14 is that any property that needs a different value in the Secure world
15 can be supported by prefixing the property name with "secure-". So for
16 instance "secure-foo" would override "foo". For property names with
17 a vendor prefix, the Secure variant of "vendor,foo" would be
[all …]
|
| D | pmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - arm,armv8-pmuv3 # Only for s/w models
24 - arm,arm1136-pmu
[all …]
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/iommu/ |
| D | qcom,iommu.txt | 3 Qualcomm "B" family devices which are not compatible with arm-smmu have
6 to non-secure vs secure interrupt line.
10 - compatible : Should be one of:
12 "qcom,msm8916-iommu"
14 Followed by "qcom,msm-iommu-v1".
16 - clock-names : Should be a pair of "iface" (required for IOMMUs
20 - clocks : Phandles for respective clocks described by
21 clock-names.
23 - #address-cells : must be 1.
25 - #size-cells : must be 1.
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/iommu/ |
| D | qcom,iommu.txt | 3 Qualcomm "B" family devices which are not compatible with arm-smmu have
6 to non-secure vs secure interrupt line.
10 - compatible : Should be one of:
12 "qcom,msm8916-iommu"
14 Followed by "qcom,msm-iommu-v1".
16 - clock-names : Should be a pair of "iface" (required for IOMMUs
20 - clocks : Phandles for respective clocks described by
21 clock-names.
23 - #address-cells : must be 1.
25 - #size-cells : must be 1.
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/nvmem/ |
| D | st,stm32-romem.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/st,stm32-romem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Factory-programmed data bindings
10 This represents STM32 Factory-programmed read only non-volatile area: locked
11 flash, OTP, read-only HW regs... This contains various information such as:
16 - Fabrice Gasnier <fabrice.gasnier@st.com>
19 - $ref: "nvmem.yaml#"
24 - st,stm32f4-otp
[all …]
|
| /kernel/linux/linux-4.19/arch/arm/common/ |
| D | secure_cntvoff.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Initialization of CNTVOFF register from secure mode
13 .arch armv7-a
15 * CNTVOFF has to be initialized either from non-secure Hypervisor
16 * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
17 * then it should be handled by the secure code. The CPU must implement
21 mrc p15, 0, r1, c1, c1, 0 /* Get Secure Config */
23 mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */
28 mcr p15, 0, r1, c1, c1, 0 /* Set Secure bit */
|
| /kernel/linux/linux-5.10/arch/arm/common/ |
| D | secure_cntvoff.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Initialization of CNTVOFF register from secure mode
13 .arch armv7-a
15 * CNTVOFF has to be initialized either from non-secure Hypervisor
16 * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
17 * then it should be handled by the secure code. The CPU must implement
21 mrc p15, 0, r1, c1, c1, 0 /* Get Secure Config */
23 mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */
28 mcr p15, 0, r1, c1, c1, 0 /* Set Secure bit */
|
| /kernel/linux/linux-4.19/arch/arm/mach-omap2/ |
| D | omap-secure.c | 2 * OMAP Secure API infrastructure.
23 #include "omap-secure.h"
28 * omap_sec_dispatcher: Routine to dispatch low power secure
33 * @arg1, arg2, arg3 args4: Parameters passed to secure API
35 * Return the non-zero error value on failure.
50 * Secure API needs physical address in omap_secure_dispatcher()
60 /* Allocate the memory to save secure ram */
98 * rx51_secure_dispatcher: Routine to dispatch secure PPA API calls
103 * @arg1, arg2, arg3 args4: Parameters passed to secure API
105 * Return the non-zero error value on failure.
[all …]
|
| D | omap-headsmp.S | 4 * Copyright (C) 2009-2014 Texas Instruments, Inc.
111 * CortexA9 r1pX and r2pX. The Control Register secure
113 * bit 0 == Secure Enable
114 * bit 1 == Non-Secure Enable
115 * The Non-Secure banked register has not changed
117 * GIC restoration will cause a problem to CPU0 Non-Secure SW.
121 * 2) CPU1 must re-enable the GIC distributor on
|
| /kernel/linux/linux-5.10/arch/arm/mach-omap2/ |
| D | omap-secure.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP Secure API infrastructure.
11 #include <linux/arm-smccc.h>
23 #include "omap-secure.h"
39 * We only check that the OP-TEE node is present and available. The in omap_optee_init_check()
40 * OP-TEE kernel driver is not needed for the type of interaction made in omap_optee_init_check()
41 * with OP-TEE here so the driver's status is not checked. in omap_optee_init_check()
50 * omap_sec_dispatcher: Routine to dispatch low power secure
55 * @arg1, arg2, arg3 args4: Parameters passed to secure API
57 * Return the non-zero error value on failure.
[all …]
|
| D | omap-headsmp.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2009-2014 Texas Instruments, Inc.
58 .arch armv7-a
110 * CortexA9 r1pX and r2pX. The Control Register secure
112 * bit 0 == Secure Enable
113 * bit 1 == Non-Secure Enable
114 * The Non-Secure banked register has not changed
116 * GIC restoration will cause a problem to CPU0 Non-Secure SW.
120 * 2) CPU1 must re-enable the GIC distributor on
|
| /kernel/linux/linux-5.10/drivers/tee/optee/ |
| D | optee_smc.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
3 * Copyright (c) 2015-2019, Linaro Limited
8 #include <linux/arm-smccc.h>
28 * Normal cached memory (write-back), shareable for SMP systems and not
36 * 32-bit registers.
44 * 65cb6b93-af0c-4617-8ed6-644a8d1140f8
75 * Used by non-secure world to figure out which Trusted OS is installed.
78 * Returns UUID in a0-4 in the same way as OPTEE_SMC_CALLS_UID
88 * Used by non-secure world to figure out which version of the Trusted OS
92 * Returns revision in a0-1 in the same way as OPTEE_SMC_CALLS_REVISION
[all …]
|
| D | optee_msg.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
3 * Copyright (c) 2015-2019, Linaro Limited
12 * This file defines the OP-TEE message protocol (ABI) used to communicate
13 * with an instance of OP-TEE running in secure world.
18 * 3. Requests from secure world, Remote Procedure Call (RPC), handled by
19 * tee-supplicant.
23 * Part 1 - formatting of messages
40 * Meta parameter to be absorbed by the Secure OS and not passed
48 * Pointer to a list of pages used to register user-defined SHM buffer.
51 * list of page addresses. OP-TEE core can reconstruct contiguous buffer from
[all …]
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/sram/ |
| D | samsung-sram.txt | 2 ------------------------------------
4 Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup
8 Therefore reserved section sub-nodes have to be added to the mmio-sram
9 declaration. These nodes are of two types depending upon secure or
10 non-secure execution environment.
12 Required sub-node properties:
13 - compatible : depending upon boot mode, should be
14 "samsung,exynos4210-sysram" : for Secure SYSRAM
15 "samsung,exynos4210-sysram-ns" : for Non-secure SYSRAM
17 The rest of the properties should follow the generic mmio-sram discription
[all …]
|
| /kernel/linux/linux-4.19/drivers/tee/optee/ |
| D | optee_smc.h | 2 * Copyright (c) 2015-2016, Linaro Limited
30 #include <linux/arm-smccc.h>
50 * Normal cached memory (write-back), shareable for SMP systems and not
58 * 32-bit registers.
66 * 65cb6b93-af0c-4617-8ed6-644a8d1140f8
97 * Used by non-secure world to figure out which Trusted OS is installed.
100 * Returns UUID in a0-4 in the same way as OPTEE_SMC_CALLS_UID
110 * Used by non-secure world to figure out which version of the Trusted OS
114 * Returns revision in a0-1 in the same way as OPTEE_SMC_CALLS_REVISION
115 * described above. May optionally return a 32-bit build identifier in a2,
[all …]
|
| D | optee_msg.h | 2 * Copyright (c) 2015-2016, Linaro Limited
34 * This file defines the OP-TEE message protocol used to communicate
35 * with an instance of OP-TEE running in secure world.
40 * 3. Requests from secure world, Remote Procedure Call (RPC), handled by
41 * tee-supplicant.
45 * Part 1 - formatting of messages
62 * Meta parameter to be absorbed by the Secure OS and not passed
70 * Pointer to a list of pages used to register user-defined SHM buffer.
73 * list of page addresses. OP-TEE core can reconstruct contiguous buffer from
85 * uint64_t pages_array[OPTEE_MSG_NONCONTIG_PAGE_SIZE/sizeof(uint64_t) - 1];
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/samsung/ |
| D | samsung-secure-firmware.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/samsung/samsung-secure-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos Secure Firmware
10 - Krzysztof Kozlowski <krzk@kernel.org>
15 - const: samsung,secure-firmware
19 Address of non-secure SYSRAM used for communication with firmware.
23 - compatible
24 - reg
[all …]
|
| /kernel/linux/linux-4.19/drivers/vfio/ |
| D | Kconfig | 22 tristate "VFIO Non-Privileged userspace driver framework"
27 VFIO provides a framework for secure userspace device drivers.
33 bool "VFIO No-IOMMU support"
38 considered secure. VFIO No-IOMMU mode enables IOMMU groups for
39 devices without IOMMU backing for the purpose of re-using the VFIO
40 infrastructure in a non-secure mode. Use of this mode will result
|
| /kernel/linux/linux-5.10/drivers/vfio/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
23 tristate "VFIO Non-Privileged userspace driver framework"
27 VFIO provides a framework for secure userspace device drivers.
28 See Documentation/driver-api/vfio.rst for more details.
33 bool "VFIO No-IOMMU support"
38 considered secure. VFIO No-IOMMU mode enables IOMMU groups for
39 devices without IOMMU backing for the purpose of re-using the VFIO
40 infrastructure in a non-secure mode. Use of this mode will result
50 source "drivers/vfio/fsl-mc/Kconfig"
|
| /kernel/linux/linux-4.19/Documentation/arm/Samsung/ |
| D | Bootloader-interface.txt | 12 In the document "boot loader" means any of following: U-boot, proprietary
17 1. Non-Secure mode
31 2. Secure mode
54 3. Other (regardless of secure/non-secure mode)
59 0x0908 Non-zero Secondary CPU boot up indicator
65 AFTR - ARM Off Top Running, a low power mode, Cortex cores and many other
67 MCPM - Multi-Cluster Power Management
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/soc/rockchip/ |
| D | grf.txt | 7 - GRF, used for general non-secure system,
8 - SGRF, used for general secure system,
9 - PMUGRF, used for always on system
14 - GRF, used for general non-secure system,
15 - SGRF, used for general secure system,
16 - DETECTGRF, used for audio codec system,
17 - COREGRF, used for pvtm,
21 - compatible: GRF should be one of the following:
22 - "rockchip,px30-grf", "syscon": for px30
23 - "rockchip,rk3036-grf", "syscon": for rk3036
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mailbox/ |
| D | arm,mhu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jassi Brar <jaswinder.singh@linaro.org>
13 The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has 3
19 be a 'Secure' resource, hence can't be used by Linux running NS.
22 interrupt signal using a 32-bit register, with all 32-bits logically ORed
28 interrupt. Each of the 32-bits can be used as "doorbell" to alert the remote
37 - arm,mhu
38 - arm,mhu-doorbell
[all …]
|
| /kernel/linux/linux-5.10/drivers/staging/wfx/ |
| D | hif_rx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Implementation of chip-to-host event (aka indications) of WFxxx Split Mac
6 * Copyright (c) 2017-2020, Silicon Laboratories, Inc.
7 * Copyright (c) 2010, ST-Ericsson
25 int cmd = hif->id; in hif_generic_confirm()
26 int len = le16_to_cpu(hif->len) - 4; // drop header in hif_generic_confirm()
28 WARN(!mutex_is_locked(&wdev->hif_cmd.lock), "data locking error"); in hif_generic_confirm()
30 if (!wdev->hif_cmd.buf_send) { in hif_generic_confirm()
31 dev_warn(wdev->dev, "unexpected confirmation: 0x%.2x\n", cmd); in hif_generic_confirm()
32 return -EINVAL; in hif_generic_confirm()
[all …]
|